Method and apparatus for a page-local delta-based prefetcher
Granted: October 8, 2024
Patent Number:
12111767
A method includes recording a first set of consecutive memory access deltas, where each of the consecutive memory access deltas represents a difference between two memory addresses accessed by an application, updating values in a prefetch training table based on the first set of memory access deltas, and predicting one or more memory addresses for prefetching responsive to a second set of consecutive memory access deltas and based on values in the prefetch training table.
Remote scalable machine check architecture
Granted: October 8, 2024
Patent Number:
12111719
An apparatus and method for supporting communication during error handling in a computing system. A computing system includes a first partition and a second partition, each capable of performing error management based on a respective machine check architecture (MCA). The first partition includes a host processor that executes an exception handler for managing reported errors. A message converter unit of the second partition assists in generating messages based on detected errors in the…
Device and method for efficient transitioning to and from reduced power state
Granted: October 8, 2024
Patent Number:
12111716
A processing device and method for efficient transitioning to and from a reduced power state is provided. The processing device comprises a plurality of components having assigned registers used to store data to execute a program and a power management controller, in communication with the plurality of components. The power management controller receives an indication that the plurality of components are idle, executes a process to enter a component into a reduced power state in response…
Adaptive out of order arbitration for numerous virtual queues
Granted: October 1, 2024
Patent Number:
12105646
A system includes a memory implementing one or more virtual queues and a processor coupled to the memory. In response to issuing one or more requests for data, a processor maps one or more of the requests for data to a return queue structure. The processor then allocates one or more virtual queues to the return queue structure based on the mapped requests. In response to allocating the virtual queues to the return queue, the processor writes the data indicated in the mapped requests to…
Through-silicon via layout for multi-die integrated circuits
Granted: October 1, 2024
Patent Number:
12107076
Integrated circuits and integrated circuit dies include TSVs laid out in symmetrical patterns. Because of the symmetrical arrangement of the TSVs and associated routing patterns, an integrated circuit is able to support operation of multiple similar dies that are placed in different positions in the integrated circuit. This in turn simplifies the design and production of the multiple similar dies, thus reducing development and manufacturing costs for the corresponding integrated…
Hybrid bonded interconnect bridging
Granted: October 1, 2024
Patent Number:
12107075
A chip for hybrid bonded interconnect bridging for chiplet integration, the chip comprising: a first chiplet; a second chiplet; an interconnecting die coupled to the first chiplet and the second chiplet through a hybrid bond.
Sampling for partially resident textures
Granted: October 1, 2024
Patent Number:
12106418
Devices, systems, and methods for sampling partially resident texture data. An instruction which includes a residency map descriptor is received. The instruction is executed to retrieve partially resident texture data from a mipmap stored in a memory based on the residency map descriptor. The residency map descriptor includes a residency map.
Accelerating relaxed remote atomics on multiple writer operations
Granted: October 1, 2024
Patent Number:
12105957
A memory controller includes an arbiter, a vector arithmetic logic unit (VALU), a read buffer and a write buffer both coupled to the VALU, and an atomic memory operation scheduler. The VALU performs scattered atomic memory operations on arrays of data elements responsive to selected memory access commands. The atomic memory operation scheduler is for scheduling atomic memory operations at the VALU; identifying a plurality of scattered atomic memory operations with commutative and…
Global addressing for switch fabric
Granted: October 1, 2024
Patent Number:
12105952
Systems, methods, and techniques are provided for a fabric addressable memory. A memory access request is received from a host computing device attached via one edge port of one or more interconnect switches, the memory access request directed to a destination segment of a physical fabric memory block that is allocated in local physical memory of the host computing device. The edge port accesses a stored mapping between segments of the physical fabric memory block and one or more…
Master-slave communication with subdomains
Granted: October 1, 2024
Patent Number:
12105666
A computing system may implement a method for creating a first subdomain by configuring one of a first plurality of slave nodes as a first subdomain master node and configuring one or more other slave nodes of the first plurality of slave nodes as first subdomain slave nodes to the first subdomain master node.
Secure testing mode
Granted: October 1, 2024
Patent Number:
12105139
A technique for operating a processing device is disclosed. The method includes irreversibly activating a testing mode switch of the processing device; in response to the activating, entering a testing mode in which normal operation of the processing device is disabled; receiving software for the processing device in the testing mode; based on whether the software is verified as testing mode-signed software, executing or not executing the software.
Cost-saving scheme for scan testing of 3D stack die
Granted: September 24, 2024
Patent Number:
12099091
A system and method for efficiently routing scan data between two dies used in three-dimensional packaging are described. In various implementations, a computing system includes at least a first semiconductor die (or first die) and a second die connected to one another within a three-dimensional (3D) package. The first die and the second die have multiple non-scan input/output (I/O) data channels between them for data transfer. The non-scan I/O data channels are partitioned into groups.…
Noise mitigation in single-ended links
Granted: September 24, 2024
Patent Number:
12101135
An integrated circuit includes a first terminal for receiving a data signal, a second terminal for receiving an external reference voltage, a receiver, and a reference voltage generation circuit. The receiver is powered by a power supply voltage with respect to ground and has a first input coupled to the first terminal, a second input for receiving a shared reference voltage, and an output for providing a data input signal. The reference voltage generation circuit is coupled to the…
Repairable latch array
Granted: September 24, 2024
Patent Number:
12100464
An integrated circuit includes a latch array including a plurality of latches logically configured in rows and columns, a plurality of repair latches operatively coupled to the plurality of latches and latch array built in self-test and repair logic (LABISTRL) coupled to the plurality of latches. In some implementations the LABISTRL configures latches in the array as one or more column serial test shift register, detects one or more defective latches of the plurality of latches based on…
Multi-kernel wavefront scheduler
Granted: September 24, 2024
Patent Number:
12099867
Systems, apparatuses, and methods for implementing a multi-kernel wavefront scheduler are disclosed. A system includes at least a parallel processor coupled to one or more memories, wherein the parallel processor includes a command processor and a plurality of compute units. The command processor launches multiple kernels for execution on the compute units. Each compute unit includes a multi-level scheduler for scheduling wavefronts from multiple kernels for execution on its execution…
Address mapping-aware tasking mechanism
Granted: September 24, 2024
Patent Number:
12099866
An Address Mapping-Aware Tasking (AMAT) mechanism manages compute task data and issues compute tasks on behalf of threads that created the compute task data. The AMAT mechanism stores compute task data generated by host threads in a set of partitions, where each partition is designated for a particular memory module. The AMAT mechanism maintains address mapping data that maps address information to partitions. Threads push compute task data to the AMAT mechanism instead of generating and…
FPGA-based programmable data analysis and compression front end for GPU
Granted: September 24, 2024
Patent Number:
12099789
Methods, devices, and systems for information communication. Information transmitted from a host to a graphics processing unit (GPU) is received by information analysis circuitry of a field-programmable gate array (FPGA). A pattern in the information is determined by the information analysis circuitry. A predicted information pattern is determined, by the information analysis circuitry, based on the information. An indication of the predicted information pattern is transmitted to the…
Tag and data configuration for fine-grained cache memory
Granted: September 24, 2024
Patent Number:
12099723
A method for operating a memory having a plurality of banks accessible in parallel, each bank including a plurality of grains accessible in parallel is provided. The method includes: based on a memory access request that specifies a memory address, identifying a set that stores data for the memory access request, wherein the set is spread across multiple grains of the plurality of grains; and performing operations to satisfy the memory access request, using entries of the set stored…
Combination BIOS with A/B recovery
Granted: September 24, 2024
Patent Number:
12099609
A computing system may implement a basic input/output system (BIOS) update method. The BIOS also includes identifying an installed central processing unit (CPU) of a computer system coupled to a BIOS chipset, selecting CPU firmware corresponding to the installed CPU from a plurality of CPU platform firmware stored on a first memory, and loading the CPU firmware into a shared portion of a second memory coupled to the BIOS chipset, where the shared portion of the second memory is…
Re-reference interval prediction (RRIP) with pseudo-LRU supplemental age information
Granted: September 24, 2024
Patent Number:
12099451
Systems and methods for cache replacement are disclosed. Techniques are described that determine a re-reference interval prediction (RRIP) value of respective data blocks in a cache, where an RRIP value represents a likelihood that a respective data block will be re-used within a time interval. Upon an access, by a processor, to a data segment in a memory, if the data segment is not stored in the cache, a data block in the cache to be replaced by the data segment is selected, utilizing a…
