Cost-saving scheme for scan testing of 3D stack die
Granted: September 24, 2024
Patent Number:
12099091
A system and method for efficiently routing scan data between two dies used in three-dimensional packaging are described. In various implementations, a computing system includes at least a first semiconductor die (or first die) and a second die connected to one another within a three-dimensional (3D) package. The first die and the second die have multiple non-scan input/output (I/O) data channels between them for data transfer. The non-scan I/O data channels are partitioned into groups.…
Semiconductor chip with redundant thru-silicon-vias
Granted: September 17, 2024
Patent Number:
12094853
A semiconductor chip with conductive vias and a method of manufacturing the same are disclosed. The method includes forming a first plurality of conductive vias in a layer of a first semiconductor chip The first plurality of conductive vias includes first ends and second ends. A first conductor pad is formed in ohmic contact with the first ends of the first plurality of conductive vias.
Shared data fabric processing client reset system and method
Granted: September 17, 2024
Patent Number:
12093689
A processing system that includes a shared data fabric resets a first client processor while operating a second client processor. The first client processor is instructed to stop making requests to one or more devices of the shared data fabric. Status communications are blocked between the first client processor and a memory controller, the second client processor, or both, such that the first client processor enters a temporary offline state. The first client processor is indicated as…
Allocation control for cache
Granted: September 17, 2024
Patent Number:
12093181
A technique for operating a cache is disclosed. The technique includes based on a workload change, identifying a first allocation permissions policy; operating the cache according to the first allocation permissions policy; based on set sampling, identifying a second allocation permissions policy; and operating the cache according to the second allocation permissions policy.
Multi-level signal reception
Granted: September 17, 2024
Patent Number:
12093124
A method for receiving a multi-level error signal having more than two logic levels includes oversampling the multi-level error signal to provide sampled symbols, wherein a first level of the multi-level error signal indicates no error, and second and third levels of the multi-level error signal indicate first and second error conditions, respectively. The sampled signals are de-serialized to provide sets of symbols. A start of a symbol period is determined in response to detecting that…
Memory sprinting
Granted: September 10, 2024
Patent Number:
12086418
A memory sprint controller, responsive to an indicator of an irregular memory access phase, causes a memory controller to enter a sprint mode in which it temporarily adjusts at least one timing parameter of a dynamic random access memory (DRAM) to reduce a time in which a designated number of activate (ACT) commands are allowed to be dispatched to the DRAM.
Clock gating using a cascaded clock gating control signal
Granted: September 10, 2024
Patent Number:
12088296
A clock circuit for clock gating using a cascaded clock gating control signal, including: a first B-latch accepting, as input, a clock gating control signal and enabled by a first clock signal; a second B-latch accepting, as input, an output from the first B-latch and enabled by a second clock signal; and a first logic outputting, based on the first B-latch, a first gated clock signal; and a second logic outputting, based on the second B-latch, a second gated clock signal.
Graphics processing unit with selective two-level binning
Granted: September 10, 2024
Patent Number:
12086899
Systems and methods related to run-time selection of a render mode in which to execute command buffers with a graphics processing unit (GPU) of a device based on performance data corresponding to the device are provided. A user mode driver (UMD) or kernel mode driver (KMD) executed at a central processing unit (CPU) selects abinning mode based on whether performance data that includes sensor data or performance counter data indicates that an associated binning condition or override…
Systems and methods for reducing instruction code memory footprint for multiple processes executed at a coprocessor
Granted: September 10, 2024
Patent Number:
12086447
A processing system includes a first processor couplable to a first memory and a second memory. In response to a page migration trigger for a page in the first memory, the first processor is configured to, responsive to the page being a read-only page storing code for execution, initiate migration of the page to a code cache portion of a second memory associated with a second processor and shared by multiple processes executing at the second processor, and to configure each process of a…
Efficient memory-semantic networking using scoped memory models
Granted: September 10, 2024
Patent Number:
12086422
A framework disclosed herein extends a relaxed, scoped memory model to a system that includes nodes across a commodity network and maintains coherency across the system. A new scope, cluster scope, is defined, that allows for memory accesses at scopes less than cluster scope to operate on locally cached versions of remote data from across the commodity network without having to issue expensive network operations. Cluster scope operations generate network commands that are used to…
Using a hardware-based controller for power state management
Granted: September 10, 2024
Patent Number:
12086009
Methods and systems are disclosed for transitioning, by a hardware-based controller, a system on a chip (SoC) into different power states. Techniques disclosed include tracking, by the controller, metrics associated with the SoC and transitioning, by the controller, the SoC from a first power state to a second power state based on the tracked metrics. Were the total amount of power that is used by at least a portion of the transition between the first power state to the second power…
Glass core package substrates
Granted: September 3, 2024
Patent Number:
12080632
Apparatuses, systems and methods for efficiently generating a package substrate. A semiconductor fabrication process (or process) fabricates each of a first glass package substrate and a second glass package substrate with a redistribution layer on a single side of a respective glass wafer. The process flips the second glass package substrate upside down and connects the glass wafers of the first and second glass package substrates together using a wafer bonding technique. In some…
Method and apparatus for providing wear leveling
Granted: September 3, 2024
Patent Number:
12080362
Exemplary embodiments provide wear spreading among die regions (i.e., one or more circuits) in an integrated circuit or among dies by using operating condition data in addition to or instead of environmental data such as temperature data, from each of a plurality of die regions. Control logic produces a cumulative amount of time each of the plurality of die regions has spent at an operating condition based on operating condition data wherein the operating condition data is based on at…
Real time on-chip texture decompression using shader processors
Granted: September 3, 2024
Patent Number:
12080032
A processing unit, method, and medium for decompressing or generating textures within a graphics processing unit (GPU). The textures are compressed with a variable-rate compression scheme such as JPEG. The compressed textures are retrieved from system memory and transferred to local cache memory on the GPU without first being decompressed. A table is utilized by the cache to locate individual blocks within the compressed texture. A decompressing shader processor receives compressed…
Bounding volume hierarchy having oriented bounding boxes with quantized rotations
Granted: September 3, 2024
Patent Number:
12079919
Described herein is a technique for performing operations for a bounding volume hierarchy. The techniques include: for a bounding box with quantized orientation, the bounding box being part of a bounding volume hierarchy, rotating a ray according to the quantized orientation to generate a rotated ray; performing an intersection test against the bounding box with the rotated ray; and according to the results of the intersection test, continuing traversal of the bounding volume hierarchy.
Look-ahead teleportation for reliable computation in multi-SIMD quantum processor
Granted: September 3, 2024
Patent Number:
12079634
A technique for processing qubits in a quantum computing device is provided. The technique includes determining that, in a first cycle, a first quantum processing region is to perform a first quantum operation that does not use a qubit that is stored in the first quantum processing region, identifying a second quantum processing region that is to perform a second quantum operation at a second cycle that is later than the first cycle, wherein the second quantum operation uses the qubit,…
Reducing power consumption associated with frequency transitioning in a memory interface
Granted: September 3, 2024
Patent Number:
12079490
Methods and systems are disclosed for frequency transitioning in a memory interface system. Techniques disclosed include receiving a signal indicative of a change in operating frequency, into a new frequency, in a processing unit interfacing with memory via the memory interface system; switching the system from a normal mode of operation into a transition mode of operation; updating control and state register (CSR) banks of respective transceivers of the system through a mission bus used…
Distribution of data and memory timing parameters across memory modules based on memory access patterns
Granted: September 3, 2024
Patent Number:
12079145
A processor distributes memory timing parameters and data among different memory modules based upon memory access patterns. The memory access patterns indicate different types, or classes, of data for an executing workload, with each class associated with different memory access characteristics, such as different row buffer hit rate levels, different frequencies of access, different criticalities, and the like. The processor assigns each memory module to a data class and sets the memory…
Debug state machine triggered extended performance monitor counter
Granted: August 27, 2024
Patent Number:
12072378
An integrated circuit (IC) includes a debug controller, a debug state machine (DSM), and an extended performance monitor counter (EPMC). The debug controller that selectively outputs debug data on a debug interconnect. The DSM identifies an event based on the debug data and an event list and outputs a DSM indication that identifies the event. The EPMC indicates a plurality of detected events including the identified event. The EPMC indicates the identified event in response to the DSM…
Scalable machine check architecture
Granted: August 27, 2024
Patent Number:
12072756
An apparatus and method for supporting communication during error handling in a computing system. A computing system includes a first partition and a second partition, each capable of performing error management based on a respective machine check architecture (MCA). When a host processor in the first partition detects an error that requires information from processor cores of the second partition, the host processor generates an access request with a target address pointing to a storage…
