Memory management in graphics and compute application programming interfaces
Granted: August 4, 2020
Patent Number:
10733696
Methods are provided for creating objects in a way that permits an API client to explicitly participate in memory management for an object created using the API. Methods for managing data object memory include requesting memory requirements for an object using an API and expressly allocating a memory location for the object based on the memory requirements. Methods are also provided for cloning objects such that a state of the object remains unchanged from the original object to the…
Method and apparatus for performing processing in a camera
Granted: July 28, 2020
Patent Number:
10728446
A method and apparatus of performing processing in an image capturing device includes receiving an image by the image capturing device. The image is filtered to generate a first visible light component and a second infrared component. A decontamination is performed on the infrared component to generate a decontaminated infrared component, and an interpolation is performed on the visible component to generate an interpolated visible component, both of which are provided to an image signal…
Power- and area-efficient clock detector
Granted: July 28, 2020
Patent Number:
10727820
A clock detector includes a first detector circuit, a second detector circuit, and a toggle detector circuit. The first detector circuit is for activating a first detect signal in response to detecting that a clock signal that toggles between first and second logic states when present is stuck in the first logic state, and keeping the first detect signal inactive otherwise. The second detector circuit is for providing a second detect signal in response to detecting that the clock signal…
VMID as a GPU task container for virtualization
Granted: July 28, 2020
Patent Number:
10725822
Systems, apparatuses, and methods for abstracting tasks in virtual memory identifier (VMID) containers are disclosed. A processor coupled to a memory executes a plurality of concurrent tasks including a first task. Responsive to detecting one or more instructions of the first task which correspond to a first operation, the processor retrieves a first identifier (ID) which is used to uniquely identify the first task, wherein the first ID is transparent to the first task. Then, the…
Method and apparatus for temperature-gradient aware data-placement for 3D stacked DRAMs
Granted: July 28, 2020
Patent Number:
10725670
A system including a stack of two or more layers of volatile memory, such as layers of a 3D stacked DRAM memory, places data in the stack based on a temperature or a refresh rate. When a threshold is exceeded, data are moved from a first region to a second region in the stack, the second region having one or both of a second temperature lower than a first temperature of the first region or a second refresh rate lower than a first refresh rate of the first region.
Using predictions of outcomes of cache memory access requests for controlling whether a request generator sends memory access requests to a memory in parallel with cache memory access requests
Granted: July 21, 2020
Patent Number:
10719441
An electronic device handles memory access requests for data in a memory. The electronic device includes a memory controller for the memory, a last-level cache memory, a request generator, and a predictor. The predictor determines a likelihood that a cache memory access request for data at a given address will hit in the last-level cache memory. Based on the likelihood, the predictor determines: whether a memory access request is to be sent by the request generator to the memory…
Heterogeneous graphics processing unit for scheduling thread groups for execution on variable width SIMD units
Granted: July 14, 2020
Patent Number:
10713059
A compute unit configured to execute multiple threads in parallel is presented. The compute unit includes one or more single instruction multiple data (SIMD) units and a fetch and decode logic. The SIMD units have differing numbers of arithmetic logic units (ALUs), such that each SIMD unit can execute a different number of threads. The fetch and decode logic is in communication with each of the SIMD units, and is configured to assign the threads to the SIMD units for execution based on…
Gate-source voltage generation for pull-up and pull-down devices in I/O designs
Granted: July 14, 2020
Patent Number:
10715139
Driver and pre-driver circuitry operate in an integrated circuit with two supply voltages. In one form, a reference voltage generation circuit is operable to respond to varying voltage supply conditions in which a driver may be subject to over voltage effects by generating a reference voltage based the first supply voltage when the second supply voltage is not available, and based on the second supply voltage when the first supply voltage is not available. A first drive signal generation…
Multi-chip package with offset 3D structure
Granted: July 14, 2020
Patent Number:
10714462
Various semiconductor chip devices and methods of manufacturing the same are disclosed. In one aspect, a semiconductor chip device is provided that has a reconstituted semiconductor chip package that includes an interposer that has a first side and a second and opposite side and a metallization stack on the first side, a first semiconductor chip on the metallization stack and at least partially encased by a dielectric layer on the metallization stack, and plural semiconductor chips…
Voltage regulation system for memory bit cells
Granted: July 14, 2020
Patent Number:
10714152
Systems, apparatuses, and methods for dynamically generating a memory bitcell supply voltage rail from a logic supply voltage rail are disclosed. A circuit includes at least one or more comparators, control logic, and power stage circuitry. The circuit receives a logic supply voltage rail and compares the logic supply voltage rail to threshold voltage(s) using the comparator(s). Comparison signal(s) from the comparator(s) are coupled to the control logic. The control logic generates mode…
Multiple-table branch target buffer
Granted: July 14, 2020
Patent Number:
10713054
A processor includes two or more branch target buffer (BTB) tables for branch prediction, each BTB table storing entries of a different target size or width or storing entries of a different branch type. Each BTB entry includes at least a tag and a target address. For certain branch types that only require a few target address bits, the respective BTB tables are narrower thereby allowing for more BTB entries in the processor separated into respective BTB tables by branch instruction…
Aligning active and idle phases in a mixed workload computing platform
Granted: July 14, 2020
Patent Number:
10712800
Systems, apparatuses, and methods for aligning active and idle phases of components in a computing system are disclosed. A computing system includes components that can be forced into an active or idle phase and components that cannot be forced into an active or idle phase. The system implements schemes for aligning the active and idle phases of the components within the system. For example, a timer starts counting when a processor and memory subsystem go from a low power state to an…
Method and system for streaming information in wireless virtual reality
Granted: July 14, 2020
Patent Number:
10712565
Described is a method and system to efficiently compress and stream texture-space rendered content that enables low latency wireless virtual reality applications. In particular, camera motion, object motion/deformation, and shading information are decoupled and each type of information is then compressed as needed and streamed separately, while taking into account its tolerance to delays.
Coherency directory entry allocation based on eviction costs
Granted: July 7, 2020
Patent Number:
10705958
A processor partitions a coherency directory into different regions for different processor cores and manages the number of entries allocated to each region based at least in part on monitored recall costs indicating expected resource costs for reallocating entries. Examples of monitored recall costs include a number of cache evictions associated with entry reallocation, the hit rate of each region of the coherency directory, and the like, or a combination thereof. By managing the…
Command processor with multiple string copy engines for a decompression system
Granted: July 7, 2020
Patent Number:
10707897
An electronic device for decompressing compressed data to recreate original data includes a first string copy engine and a second string copy engine. The first string copy engine processes a first string copy command by acquiring a first string from recreated original data and appending the first string to the recreated original data. The second string copy engine processes a second string copy command by checking the second string copy command for a dependency on the first string and,…
Image generation based on brain activity monitoring
Granted: July 7, 2020
Patent Number:
10706631
Systems, methods, and devices for generating an image frame for display to a user. Brain activity sensor data correlated with movement of a user is received. A predicted field of view of the user is determined based on the brain activity sensor data. An image frame is generated based on the predicted field of view. The image frame is transmitted to a display for display to a user. Some implementations provide for receiving and displaying a foveated image frame based on a predicted field…
Efficient data path for ray triangle intersection
Granted: July 7, 2020
Patent Number:
10706609
Described herein is a technique for performing ray-triangle intersection without a floating point division unit. A division unit would be useful for a straightforward implementation of a certain type of ray-triangle intersection test that is useful in ray tracing operations. This certain type of ray-triangle intersection test includes a step that transforms the coordinate system into the viewspace of the ray, thereby reducing the problem of intersection to one of 2D triangle…
Bucketized hash tables with remap entries
Granted: July 7, 2020
Patent Number:
10706101
Methods and mechanisms for managing data in a hash table are disclosed. A computing system includes a hash table configured to store data and hash management logic. In response to receiving a request to insert data into the hash table, the hash management logic is configured to generate a first hash value by applying a first hash function to the key of the key-value pair, and identify a first bucket within the hash table that corresponds to the first hash table. If the first bucket has a…
Dynamic adaptation of memory page management policy
Granted: July 7, 2020
Patent Number:
10705972
Systems, apparatuses, and methods for determining preferred memory page management policies by software are disclosed. Software executing on one or more processing units generates a memory request. Software determines the preferred page management policy for the memory request based at least in part on the data access size and data access pattern of the memory request. Software conveys an indication of a preferred page management policy to a memory controller. Then, the memory controller…
Region based split-directory scheme to adapt to large cache sizes
Granted: July 7, 2020
Patent Number:
10705959
Systems, apparatuses, and methods for maintaining region-based cache directories split between node and memory are disclosed. The system with multiple processing nodes includes cache directories split between the nodes and memory to help manage cache coherency among the nodes' cache subsystems. In order to reduce the number of entries in the cache directories, the cache directories track coherency on a region basis rather than on a cache line basis, wherein a region includes multiple…
