Scheduling memory bandwidth based on quality of service floorbackground
Granted: June 30, 2020
Patent Number:
10700954
A system includes a multi-core processor that includes a scheduler. The multi-core processor communicates with a system memory and an operating system. The multi-core processor executes a first process and a second process. The system uses the scheduler to control a use of a memory bandwidth by the second process until a current use in a control cycle by the first process meets a first setpoint of use for the first process when the first setpoint is at or below a latency sensitive (LS)…
Graphics library extensions
Granted: June 30, 2020
Patent Number:
10699464
Methods for enabling graphics features in processors are described herein. Methods are provided to enable trinary built-in functions in the shader, allow separation of the graphics processor's address space from the requirement that all textures must be physically backed, enable use of a sparse buffer allocated in virtual memory, allow a reference value used for stencil test to be generated and exported from a fragment shader, provide support for use specific operations in the stencil…
Secure enablement of platform features without user intervention
Granted: June 30, 2020
Patent Number:
10699033
Systems, apparatuses, and methods for secure enablement of platform features without user intervention are disclosed. In one embodiment, a system includes at least a motherboard and a processor. The motherboard includes at least a socket and an authentication component. The authentication component can be a chipset, expansion I/O device, or other component. The processor is installed in the socket on the motherboard. During a boot sequence, the processor retrieves a key value from the…
Alternative protocol selection
Granted: June 30, 2020
Patent Number:
10698856
A link controller, method, and data processing platform are provided with dual-protocol capability. The link controller includes a physical layer circuit for providing a data lane over a communication link, a first data link layer controller which operates according to a first protocol, and a second data link layer controller which operates according to a second protocol. A multiplexer/demultiplexer selectively connects both data link layer controllers to the physical layer circuit. A…
Controlling the operating speed of stages of an asynchronous pipeline
Granted: June 30, 2020
Patent Number:
10698692
An asynchronous pipeline includes a first stage and one or more second stages. A controller provides control signals to the first stage to indicate a modification to an operating speed of the first stage. The modification is determined based on a comparison of a completion status of the first stage to one or more completion statuses of the one or more second stages. In some cases, the controller provides control signals indicating modifications to an operating voltage applied to the…
Method and device for determining branch prediction history for branch prediction by partially combining shifted branch prediction history with branch signature
Granted: June 30, 2020
Patent Number:
10698691
Disclosed are a method and a processing device directed to determining global branch history for branch prediction. The method includes shifting first bits of a branch signature into a current global branch history and performing a bitwise exclusive-or (XOR) function on second bits of the branch signature and shifted bits of the current global branch history. In this way, the current global branch history is updated. The processing device implements the method using a shift logic…
Instruction subset implementation for low power operation
Granted: June 30, 2020
Patent Number:
10698472
A heterogeneous processor system includes a first processor implementing an instruction set architecture (ISA) including a set of ISA features and configured to support a first subset of the set of ISA features. The heterogeneous processor system also includes a second processor implementing the ISA including the set of ISA features and configured to support a second subset of the set of ISA features, wherein the first subset and the second subset of the set of ISA features are different…
High-performance sparse triangular solve on graphics processing units
Granted: June 23, 2020
Patent Number:
10691772
A method includes storing a sparse triangular matrix as a compressed sparse row (CSR) dataset. For each factor of a plurality of factors in a first vector, a value of the factor is calculated by identifying for the factor a set of one or more antecedent factors in the first vector, where the value of the factor is dependent on each of the one or more antecedent factors. In response to a completion array indicating that all of the one or more antecedent factor values are solved, the value…
Low power VTT generation mechanism for receiver termination
Granted: June 23, 2020
Patent Number:
10692545
Systems, apparatuses, and methods for performing efficient data transfer in a computing system are disclosed. A termination voltage generator includes an inverter-based chopper circuit, which uses a first group of an even number of serially connected inverters coupled between the output node of the chopper circuit and the gate terminal of an output pmos transistor. Additionally, a second group of an even number of serially connected inverters is coupled between the output node and the…
Robust ray-triangle intersection
Granted: June 23, 2020
Patent Number:
10692271
A technique for classifying a ray tracing intersection with a triangle edge or vertex avoids either rendering holes or multiple hits of the same ray for different triangles. The technique employs a tie-breaking scheme in which certain types of edges are classified as hits and certain types of edges are classified as misses. The test is performed in a coordinate space that comprises a projection into the viewspace of the ray, and thus where the ray direction has a non-zero magnitude in…
Command arbitration for high speed memory interfaces
Granted: June 16, 2020
Patent Number:
10684969
In one form, a memory controller includes a command queue and an arbiter. The command queue receives and stores memory access requests. The arbiter includes a plurality of sub-arbiters for providing a corresponding plurality of sub-arbitration winners from among the memory access requests during a controller cycle, and for selecting among the plurality of sub-arbitration winners to provide a plurality of memory commands in a corresponding controller cycle. In another form, a data…
Method to reduce write responses to improve bandwidth and efficiency
Granted: June 16, 2020
Patent Number:
10684965
Systems, apparatuses, and methods for routing traffic between clients and system memory are disclosed. A computing system includes system memory and one or more clients, each capable of generating memory access requests. The computing system also includes a communication fabric for transferring traffic between the clients and the system memory. The fabric includes master units for interfacing with clients and grouping write requests with a same target together. The fabric also includes…
Apparatus and method for neighborhood-aware virtual to physical address translations
Granted: June 16, 2020
Patent Number:
10684957
An apparatus and method performs neighborhood-aware virtual to physical address translations. A coalescing opportunity for a first virtual address is determined, based on completing a memory access corresponding to a page walk for a second virtual address. Metadata corresponding to the first virtual address is provided to a page table walk buffer based on the coalescing opportunity and a page walk for the first virtual address is performed based on the metadata corresponding to the first…
Method and apparatus for memory vulnerability prediction
Granted: June 16, 2020
Patent Number:
10684902
Described herein are a method and apparatus for memory vulnerability prediction. A memory vulnerability predictor predicts the reliability of a memory region when it is first accessed, based on past program history. The memory vulnerability predictor uses a table to store reliability predictions and predicts reliability needs of a new memory region. A memory management module uses the reliability information to make decisions, (such as to guide memory placement policies in a…
Systems and methods of supporting parallel processor message-based communications
Granted: June 9, 2020
Patent Number:
10681125
A method of message-based communication is provided which includes executing, on one or more accelerated processing units, a plurality of groups of work items, receiving a first message from a first group of work items of the plurality of groups of work items executing on the one or more accelerated processing units and storing the first message at a first segment of memory allocated to a second group of work items of the plurality of groups of work items executing on the accelerated…
Adaptive beam assessment to predict available link bandwidth
Granted: June 9, 2020
Patent Number:
10680927
Systems, apparatuses, and methods for dynamically adjusting data bandwidth to fit a predicted available bandwidth of a link are disclosed. A system includes a transmitter and a receiver communicating wirelessly over a wireless link. The system monitors a status of the wireless link at a plurality of points in time. The system trains a predictive model using a plurality of indicators of the status of the link at the plurality of points in time. The model generates a prediction of the…
Single pass prefix sum in a vertex shader
Granted: June 9, 2020
Patent Number:
10679316
Systems, apparatuses, and methods for implementing a single pass stipple pattern generation process are disclosed. A processor initiates parallel execution of a first and second plurality of wavefronts. A first wavefront of the first plurality of wavefronts converts a first local coordinate into a first global coordinate, wherein the first local coordinate corresponds to a first portion of a primitive. Also, a first wavefront of the second plurality of wavefronts applies a first…
Using multiple memory elements in an input-output memory management unit for performing virtual address to physical address translations
Granted: June 9, 2020
Patent Number:
10678702
The described embodiments include an input-output memory management unit (IOMMU) with two or more memory elements and a controller. The controller is configured to select, based on one or more factors, one or more selected memory elements from among the two or more memory elements for performing virtual address to physical address translations in the IOMMU. The controller then performs the virtual address to physical address translations using the one or more selected memory elements.
Multi-node system low power management
Granted: June 2, 2020
Patent Number:
10671148
Systems, apparatuses, and methods for performing efficient power management for a multi-node computing system are disclosed. A computing system including multiple nodes utilizes a non-uniform memory access (NUMA) architecture. A first node receives a broadcast probe from a second node. The first node spoofs a miss response for a powered down third node, which prevents the third node from waking up to respond to the broadcast probe. Prior to powering down, the third node flushed its probe…
Monitoring of memory page transitions between a hypervisor and a virtual machine
Granted: June 2, 2020
Patent Number:
10671422
A security module in a memory access path of a processor of a processing system protects secure information by verifying the contents of memory pages as they transition between one or more virtual machines (VMs) executing at the processor and a hypervisor that provides an interface between the VMs and the processing system's hardware. The security module of the processor is employed to monitor memory pages as they transition between one or more VMs and a hypervisor so that memory pages…
