Forward rendering pipeline with light culling
Granted: November 5, 2024
Patent Number:
12136165
A method for enhanced forward rendering is disclosed which includes a depth pre-pass, light culling and a final shading. The depth pre-pass minimizes the cost of final shading by avoiding high pixel overdraw. The light culling stage calculates a list of light indices overlapping a pixel. The light indices are calculated on a per-tile basis, where the screen has been split into units of tiles. The final shading evaluates materials using information stored for each light. The forward…
Flexible dictionary sharing for compressed caches
Granted: November 5, 2024
Patent Number:
12135653
Systems, apparatuses, and methods for implementing flexible dictionary sharing techniques for caches are disclosed. A set-associative cache includes a dictionary for each data array set. When a cache line is to be allocated in the cache, a cache controller determines to which set a base index of the cache line address maps. Then, a selector unit determines which dictionary of a group of dictionaries stored by those sets neighboring this set would achieve the most compression for the…
Residue-code-based error detection for cipher generation
Granted: October 29, 2024
Patent Number:
12130701
A processing unit employs a residue code (RC) to perform error detection and correction for a multi-round transformation data encryption process. The processing unit generates a cipher based on a plurality of transformations. For each of the plurality of transformations, the processing unit generates a corresponding residue code of a plurality of residue codes. The processing unit performs error detection for the cipher based on the plurality of residue codes.
Apparatus, system, and method for calibrating high-speed communication interfaces to transmission lines
Granted: October 29, 2024
Patent Number:
12132460
A computing device for calibrating high-speed communication interfaces to transmission lines may include an impedance-matching driver with a plurality of independently controllable impedance stages that facilitate matching an impedance of a transmission line. The computing device may also include a controller communicatively coupled to the impedance-matching driver via a plurality of control signals grouped into a first group of control signals that control a first stage included in the…
Workgroup synchronization and processing
Granted: October 29, 2024
Patent Number:
12131199
A processing system monitors and synchronizes parallel execution of workgroups (WGs). One or more of the WGs perform (e.g., periodically or in response to a trigger such as an indication of oversubscription) a waiting atomic instruction. In response to a comparison between an atomic value produced as a result of the waiting atomic instruction and an expected value, WGs that fail to produce a correct atomic value are identified as being in a waiting state (e.g., waiting for a…
Hardware accelerated dynamic work creation on a graphics processing unit
Granted: October 29, 2024
Patent Number:
12131186
A processor core is configured to execute a parent task that is described by a data structure stored in a memory. A coprocessor is configured to dispatch a child task to the at least one processor core in response to the coprocessor receiving a request from the parent task concurrently with the parent task executing on the at least one processor core. In some cases, the parent task registers the child task in a task pool and the child task is a future task that is configured to monitor a…
Methods and apparatus for offloading tiered memories management
Granted: October 29, 2024
Patent Number:
12131063
Methods and apparatus offload tiered memories management. The method includes obtaining a pointer to a stored memory management structure associated with tiered memories, where the memory management structure includes a plurality of memory management entries and each memory management entry of the plurality of memory management entries includes information for a memory section in one of the tiered memories. In some instances, the method includes scanning at least a part of the plurality…
Adaptive scheduling of memory and processing-in-memory requests
Granted: October 29, 2024
Patent Number:
12131026
Adaptive scheduling of memory requests and processing-in-memory requests is described. In accordance with the described techniques, a memory controller receives a plurality of processing-in-memory requests and a plurality of non-processing-in-memory requests from a host. The memory controller schedules an order of execution for the plurality of processing-in-memory requests and the plurality of non-processing-in-memory requests based at least in part on a processing-in-memory request…
Resource-aware compression
Granted: October 29, 2024
Patent Number:
12130741
Systems, apparatuses, and methods for implementing a multi-tiered approach to cache compression are disclosed. A cache includes a cache controller, light compressor, and heavy compressor. The decision on which compressor to use for compressing cache lines is made based on certain resource availability such as cache capacity or memory bandwidth. This allows the cache to opportunistically use complex algorithms for compression while limiting the adverse effects of high decompression…
Autonomous organization and role selection of homogenous workers
Granted: October 29, 2024
Patent Number:
12130713
A method for configuring replicas in a distributed computing system is disclosed. In one example embodiment, a plurality of replicas with associated bootstrap modules may be created. The same bootstrap module code may be used for each replica, thereby simplifying configuration. Using the bootstrap module, the replicas may automatically configure themselves and self-assign a role for a set of predetermined roles such as master and worker. The bootstrap module may check a predetermined…
Low power state selection based on idle duration history
Granted: October 29, 2024
Patent Number:
12130692
An apparatus includes a processor, a sleep state duration prediction module, and a system management unit. The sleep state duration prediction module is configured to predict a sleep state duration for component of the processing device. The system management unit is to transition the component into a sleep state selected from a plurality of sleep states based on a comparison of the predicted sleep state duration to at least one duration threshold. Each sleep state of the plurality of…
Technique for extended idle duration for display to improve power consumption
Granted: October 29, 2024
Patent Number:
12130690
A method and system for operating in a single display mode operation and a dual pipe mode of operation is disclosed. The method and system includes operating in a dual pipe mode of operation in which each display pipe transmits data from a respective buffer to an associated display. The method and system further includes operating in a single display mode of operation in which one display pipe transmits data from a plurality of buffers to an associated display.
System and method for providing page migration
Granted: October 22, 2024
Patent Number:
12124865
Methods and apparatus for providing page migration of pages among tiered memories identify frequently accessed memory pages in each memory tier and generate page hotness ranking information indicating how frequently memory pages are being accessed. Methods and apparatus provide the page hotness ranking information to an operating system or hypervisor depending on which is used in the system, the operating system or hypervisor issues a page move command to a hardware data mover, based on…
Handling engineering change orders for integrated circuits in a design
Granted: October 22, 2024
Patent Number:
12124788
A method for handling engineering change orders (ECOs) for an integrated circuit design is described herein. An ECO program performs operations for an ECO flow. The ECO flow includes the ECO program generating a changed design by applying ECO changes for a set of ECOs to integrated circuits in an initial design. The ECO program then finds ECO change rule violations for the changed design. The ECO program next identifies selected ECOs associated with ECO change rule violations. The ECO…
Device and method for accelerating matrix multiply operations
Granted: October 22, 2024
Patent Number:
12124531
A processing device including a plurality of clusters of processor cores and a method for use in the processing device is disclosed. Each processor core in a cluster of processor cores is in communication with the other processor cores in the cluster and at least one processor core of each cluster is in communication with at least a processor core of a different cluster of processor cores. Each processor core is configured to store a product of a portion of a first matrix and a first…
Method and apparatus for controlling cache line storage in cache memory
Granted: October 22, 2024
Patent Number:
12124373
A method and apparatus physically partitions clean and dirty cache lines into separate memory partitions, such as one or more banks, so that during low power operation, a cache memory controller reduces power consumption of the cache memory containing the clean only data. The cache memory controller controls refresh operation so that data refresh does not occur for clean data only banks or the refresh rate is reduced for clean data only banks. Partitions that store dirty data can also…
Dynamic voltage frequency scaling based on active memory barriers
Granted: October 22, 2024
Patent Number:
12124311
A processing unit includes compute units partitioned into one or islands that are provided with operating voltages and clock signals having clock frequencies independent of providing operating voltages or clock signals to other islands of compute units. The processing unit also includes dynamic voltage and frequency scaling (DVFS) hardware configured to compute one or more numbers of active memory barriers in the one or more islands. The DVFS hardware is also configured to modify the…
Memory controller with pseudo-channel support
Granted: October 15, 2024
Patent Number:
12117945
A data processor accesses a memory having a first pseudo channel and a second pseudo channel. The data processor includes at least one memory accessing agent for generating a memory access request, a memory controller for providing a memory command to the memory in response to a normalized request selectively using a first pseudo channel pipeline circuit and a second pseudo channel pipeline circuit, and a data fabric for converting the memory access request into the normalized request…
Virtually padding data structures
Granted: October 15, 2024
Patent Number:
12118354
A virtual padding unit provides a virtual padded data structure (e.g., virtually padded matrix) that provides output values for a padded data structure without storing all of the padding elements in memory. When the virtual padding unit receives a virtual memory address of a location in the virtual padded data structure, the virtual padding unit checks whether the location is a non-padded location in the virtual padded data structure or a padded location in the virtual padded data…
Performance of bank refresh
Granted: October 15, 2024
Patent Number:
12118247
A memory controller includes an arbiter. The arbiter is configured to elevate a priority of memory access requests that generate row activate commands in response to receiving a same-bank refresh request, and to send a same-bank refresh command in response to receiving the same-bank refresh request.
