Distributed scheduler providing execution pipe balance
Granted: October 15, 2024
Patent Number:
12118411
A processor includes a plurality of execution pipes and a distributed scheduler coupled to the plurality of execution pipes. The distributed scheduler includes a first queue to buffer instruction operations from a front end of an instruction pipeline of the processor and a plurality of second queues, wherein each second queue is to buffer instruction operations allocated from the first queue for a corresponding separate subset of execution pipes of the plurality of execution pipes. The…
Encoded data dependency matrix for power efficiency scheduling
Granted: October 15, 2024
Patent Number:
12118357
The disclosed system may include a processor configured to encode, using an encoding scheme that reduces a number of bits needed to represent one or more instructions from a set of instructions in an instruction buffer represented by a dependency matrix, a dependency indicating that a child instruction represented in the dependency matrix depends on a parent instruction represented in the dependency matrix. The processor may also be configured to store the encoded dependency in the…
Virtually padding data structures
Granted: October 15, 2024
Patent Number:
12118354
A virtual padding unit provides a virtual padded data structure (e.g., virtually padded matrix) that provides output values for a padded data structure without storing all of the padding elements in memory. When the virtual padding unit receives a virtual memory address of a location in the virtual padded data structure, the virtual padding unit checks whether the location is a non-padded location in the virtual padded data structure or a padded location in the virtual padded data…
Performance of bank refresh
Granted: October 15, 2024
Patent Number:
12118247
A memory controller includes an arbiter. The arbiter is configured to elevate a priority of memory access requests that generate row activate commands in response to receiving a same-bank refresh request, and to send a same-bank refresh command in response to receiving the same-bank refresh request.
Memory controller with pseudo-channel support
Granted: October 15, 2024
Patent Number:
12117945
A data processor accesses a memory having a first pseudo channel and a second pseudo channel. The data processor includes at least one memory accessing agent for generating a memory access request, a memory controller for providing a memory command to the memory in response to a normalized request selectively using a first pseudo channel pipeline circuit and a second pseudo channel pipeline circuit, and a data fabric for converting the memory access request into the normalized request…
Stochastic optimization of surface cacheability in parallel processing units
Granted: October 15, 2024
Patent Number:
12117939
A processing system selectively allocates storage at a local cache of a parallel processing unit for cache lines of a repeating pattern of data that exceeds the storage capacity of the cache. The processing system identifies repeating patterns of data having cache lines that have a reuse distance that exceeds the storage capacity of the cache. A cache controller allocates storage for only a subset of cache lines of the repeating pattern of data at the cache and excludes the remainder of…
Technique to enable simultaneous use of on-die SRAM as cache and memory
Granted: October 15, 2024
Patent Number:
12117935
A technique for operating a cache is disclosed. The technique includes utilizing a first portion of a cache in a directly accessed manner; and utilizing a second portion of the cache as a cache.
Techniques for supporting large frame buffer apertures with better system compatibility
Granted: October 15, 2024
Patent Number:
12117933
A technique for accessing accelerated processing device (“APD”) memory is provided. The technique includes identifying whether to activate one or both of a first direct mapping unit and a second direct mapping unit, wherein the first direct mapping unit is associated with a small address size and the second direct mapping unit is associated with a large address size; activating the identified one or both of the first direct mapping unit and the second direct mapping unit; and…
Dynamic network-on-chip throttling
Granted: October 8, 2024
Patent Number:
12113712
Dynamic network-on-chip traffic throttling, including: determining, by a detector module of a network-on-chip, that a predefined condition is met; sending, by the detector module, a signal to a mediator module of the network-on-chip; and sending, in response to the signal, by the mediator module, an indication to a plurality of agents to implement a traffic throttling policy.
Buffer management for plug-in architectures in computation graph structures
Granted: October 8, 2024
Patent Number:
12113946
A computer vision processing device is provided which comprises memory configured to store data and a processor. The processor is configured to store captured image data in a first buffer and acquire access to the captured image data in the first buffer when the captured image data is available for processing. The processor is also configured to execute a first group of operations in a processing pipeline, each of which processes the captured image data accessed from the first buffer and…
Deliberate conditional poison training for generative models
Granted: October 8, 2024
Patent Number:
12112270
A generator for generating artificial data, and training for the same. Data corresponding to a first label is altered within a reference labeled data set. A discriminator is trained based on the reference labeled data set to create a selectively poisoned discriminator. A generator is trained based on the selectively poisoned discriminator to create a selectively poisoned generator. The selectively poisoned generator is tested for the first label and tested for the second label to…
Method and apparatus for a page-local delta-based prefetcher
Granted: October 8, 2024
Patent Number:
12111767
A method includes recording a first set of consecutive memory access deltas, where each of the consecutive memory access deltas represents a difference between two memory addresses accessed by an application, updating values in a prefetch training table based on the first set of memory access deltas, and predicting one or more memory addresses for prefetching responsive to a second set of consecutive memory access deltas and based on values in the prefetch training table.
Remote scalable machine check architecture
Granted: October 8, 2024
Patent Number:
12111719
An apparatus and method for supporting communication during error handling in a computing system. A computing system includes a first partition and a second partition, each capable of performing error management based on a respective machine check architecture (MCA). The first partition includes a host processor that executes an exception handler for managing reported errors. A message converter unit of the second partition assists in generating messages based on detected errors in the…
Device and method for efficient transitioning to and from reduced power state
Granted: October 8, 2024
Patent Number:
12111716
A processing device and method for efficient transitioning to and from a reduced power state is provided. The processing device comprises a plurality of components having assigned registers used to store data to execute a program and a power management controller, in communication with the plurality of components. The power management controller receives an indication that the plurality of components are idle, executes a process to enter a component into a reduced power state in response…
Secure testing mode
Granted: October 1, 2024
Patent Number:
12105139
A technique for operating a processing device is disclosed. The method includes irreversibly activating a testing mode switch of the processing device; in response to the activating, entering a testing mode in which normal operation of the processing device is disabled; receiving software for the processing device in the testing mode; based on whether the software is verified as testing mode-signed software, executing or not executing the software.
Through-silicon via layout for multi-die integrated circuits
Granted: October 1, 2024
Patent Number:
12107076
Integrated circuits and integrated circuit dies include TSVs laid out in symmetrical patterns. Because of the symmetrical arrangement of the TSVs and associated routing patterns, an integrated circuit is able to support operation of multiple similar dies that are placed in different positions in the integrated circuit. This in turn simplifies the design and production of the multiple similar dies, thus reducing development and manufacturing costs for the corresponding integrated…
Sampling for partially resident textures
Granted: October 1, 2024
Patent Number:
12106418
Devices, systems, and methods for sampling partially resident texture data. An instruction which includes a residency map descriptor is received. The instruction is executed to retrieve partially resident texture data from a mipmap stored in a memory based on the residency map descriptor. The residency map descriptor includes a residency map.
Global addressing for switch fabric
Granted: October 1, 2024
Patent Number:
12105952
Systems, methods, and techniques are provided for a fabric addressable memory. A memory access request is received from a host computing device attached via one edge port of one or more interconnect switches, the memory access request directed to a destination segment of a physical fabric memory block that is allocated in local physical memory of the host computing device. The edge port accesses a stored mapping between segments of the physical fabric memory block and one or more…
Master-slave communication with subdomains
Granted: October 1, 2024
Patent Number:
12105666
A computing system may implement a method for creating a first subdomain by configuring one of a first plurality of slave nodes as a first subdomain master node and configuring one or more other slave nodes of the first plurality of slave nodes as first subdomain slave nodes to the first subdomain master node.
Adaptive out of order arbitration for numerous virtual queues
Granted: October 1, 2024
Patent Number:
12105646
A system includes a memory implementing one or more virtual queues and a processor coupled to the memory. In response to issuing one or more requests for data, a processor maps one or more of the requests for data to a return queue structure. The processor then allocates one or more virtual queues to the return queue structure based on the mapped requests. In response to allocating the virtual queues to the return queue, the processor writes the data indicated in the mapped requests to…
