SOFT TOUCH COATING MATERIALS FOR SUBSTRATE HANDLING
Granted: May 8, 2025
Application Number:
20250149373
Semiconductor components and systems having substrate contacting surfaces with a reduced hardness are provided. Systems and components include a ceramic, metallic, or non-metallic component for contacting a substrate. Systems and components include a layer of coating material on at least a portion of a substrate contacting surface of the component. Systems and components include where the component for contacting a substrate includes a component Vickers hardness value, and the layer of…
CENTERING WAFER FOR PROCESSING CHAMBER
Granted: May 8, 2025
Application Number:
20250149367
Processing chambers, substrate supports, centering wafers and methods of center calibrating wafer hand-off are described. A centering wafer comprises a disc-shaped body having a top surface and a bottom surface defining a thickness, a center, an outer edge having an outer peripheral face, a first arc-shaped slit and a second arc-shaped slit. Embodiments of the disclosure advantageously provide the ability to use the centering wafer to monitor and control backside pressure and thereby…
VIBRATION REDUCTION IN ION IMPLANTERS USING EMBEDDED ACTUATOR FORCED ATTENUATION
Granted: May 8, 2025
Application Number:
20250144669
A vibrating actuator adapted to be installed within a component of an ion implanter, the vibrating actuator including a housing defining an internal cavity, and a vibrating mechanism disposed within the internal cavity, the vibrating mechanism including an actuating element and a vibratory element coupled to the actuating element, wherein when an electrical signal is applied to the actuating element, the actuating element moves the vibratory element to vibrate the housing.
N-CHANNEL COUPLED WITH P-CHANNEL AND METHODS OF MANUFACTURE
Granted: May 1, 2025
Application Number:
20250142957
Logic devices and methods of manufacturing logic devices are provided. The semiconductor logic device includes an n-channel gate-all-around (n-GAA) field-effect transistor on a substrate integrated with a p-channel gate-all-around (p-GAA) field-effect transistor on the substrate adjacent to the n-channel gate-all-around (p-GAA) field-effect transistor. The n-channel gate-all-around (n-GAA) field effect-transistor has a structure including a plurality of layers comprising silicon and a…
CONDUIT, SYSTEMS AND METHODS FOR FLUID TEMPERATURE CONTROL
Granted: May 1, 2025
Application Number:
20250135423
Chemical deliver conduits, systems for substrate processing and methods for supplying a chemical to a substrate processing chamber are described. The conduit has a length and connects a vessel containing the chemical to the substrate processing chamber. The conduit comprises an outer channel surrounding an inner channel. The outer channel is in fluid communication with source of a heat transfer fluid, and the inner channel is in fluid communication with the vessel containing the…
DUAL CHANNEL SHOWERHEAD CONDUCTANCE OPTIMIZATION FOR UNIFORM RADIAL FLOW DISTRIBUTION
Granted: May 1, 2025
Application Number:
20250135473
A dual-channel showerhead may include a first plate defining two or more channels and a second plate including a bottom surface and defining a plurality of apertures. Each of the two or more channels may be fluidly coupled with one of the plurality of apertures to define a fluid path extending from the first plate through the bottom surface. The plurality of apertures may be arranged in a series of rings. A first subset of apertures of the plurality of apertures may extend through the…
DYNAMIC ION BEAM SHAPE SELECTION
Granted: May 1, 2025
Application Number:
20250140510
Techniques to dynamically tune components of an ion implanter are described. A method includes generating a first histogram for a first setting parameter of an ion implanter and a second histogram for a second setting parameter of the ion implanter. The histograms comprise a graphical representation of a distribution of data points across a range of values for each setting parameter. The method includes presenting the histograms on a user interface, receiving a control directive to…
SUBSTRATE STRESS MANAGEMENT USING VARIABLE ENERGY AND VARIABLE DOSE IMPLANTATION
Granted: May 1, 2025
Application Number:
20250140523
A method of stress management in a substrate. The method may include comprising providing a stress compensation layer on a main surface of the substrate; and performing a dynamic implant procedure in an ion implanter to implant a set of ions into the stress compensation layer. The dynamic implant procedure may include exposing the substrate to an ion beam under a first set of conditions, the first set of conditions comprising an ion energy, a beam scan rate and a substrate scan rate; and…
CHAMBER AND METHODS FOR DOWNSTREAM RESIDUE MANAGEMENT
Granted: May 1, 2025
Application Number:
20250140537
Semiconductor processing chambers and systems, as well as methods of cleaning such chambers and systems are provided. Processing chambers and systems include a chamber body that defines a processing region, a liner positioned within the chamber body that defines a liner volume, a faceplate positioned atop the liner, a substrate support disposed within the chamber body, and a cleaning gas source coupled with the liner volume through a cleaning gas plenum and one or more inlet apertures.…
LOW RESISTIVITY METAL STACKS AND METHODS OF DEPOSITING THE SAME
Granted: May 1, 2025
Application Number:
20250140562
Metal stacks and methods of depositing a metal stack on a semiconductor substrate are disclosed. The metal stack is formed by depositing a tungsten (W) layer on the semiconductor substrate and depositing a molybdenum (Mo) layer on the tungsten (W) layer. In one method, a tungsten (W) capping layer is deposited on the molybdenum (Mo) layer, followed by formation of a nitride capping layer on the tungsten (W) capping layer). In a second method, a nitride capping layer is formed on the…
SELECTIVITY OF BORON HARD MASKS USING ION IMPLANT
Granted: May 1, 2025
Application Number:
20250140566
Thicker hardmasks are typically needed for etching deeper capacitor holes in a DRAM structure. Instead of increasing the hardmask thickness, hardmasks may instead be formed with an increased etch selectivity relative to the underlying semiconductor structure. For example, boron-based hardmasks may be formed that include a relatively high percentage of boron (e.g., greater than 90%). The etch selectivity of the hardmask may be improved by performing an ion implant process using different…
MULTI-PARAMETER IMPLANTATION FOR MANAGING WAFER DISTORTION
Granted: May 1, 2025
Application Number:
20250140567
A a method of stress management in a substrate. The method may include providing a stress compensation layer on a main surface of the substrate; and performing a chained implant procedure to implant a set of ions into the stress compensation layer. The chained implant procedure may include directing a first implant procedure to the substrate, the first implant procedure generating a first damage profile within the stress compensation layer; directing a second implant to the substrate,…
LOCALIZED STRESS MODULATION BY IMPLANT TO BACK OF WAFER
Granted: May 1, 2025
Application Number:
20250140569
Embodiments herein are directed to localized stress modulation by implanting a first side of a substrate to reduce in-plane distortion along a second side of the substrate. In some embodiments, a method may include providing a substrate, the substrate comprising a first main side opposite a second main side, wherein a plurality of features are disposed on the first main side, performing a metrology scan to the first main side to determine an amount of distortion to the substrate due to…
VIA SHAPING BETWEEN METAL LAYERS FOR CONTROLLED RESISTANCE
Granted: May 1, 2025
Application Number:
20250140604
This disclosure describes structures and methods for forming tapered vias between features in metal layers in semiconductor devices. Instead of straight vias that have 90° vertical sidewalls and a constant cross-sectional area throughout the height of the via, tapered vias may be formed that extend outward from one metal layer to a lower metal layer. The via may be allowed to expand in size in a direction parallel to the feature in the lower metal layer, while remaining a constant width…
NON-DESTRUCTIVE THREE-DIMENSIONAL PROBING AND CHARACTERIZATION OF SPECIMENS
Granted: April 24, 2025
Application Number:
20250130185
Disclosed herein is a system for non-destructive characterization of specimens. The system includes an electron beam (e-beam) source for projecting e-beams at one or more e-beam landing energies on a specimen; an X-ray detector for sensing X-rays emitted from the specimen, thereby obtaining measurement data; and a processing circuitry. The processing circuitry is configured to: (i) extract from the measurement data key features specified by a vector {right arrow over (f)}key; and (ii)…
SELECTIVE ETCHING OF SCANDIUM-DOPED ALUMINUM NITRIDE
Granted: April 24, 2025
Application Number:
20250133965
Exemplary substrate processing methods are described. The methods may include providing a scandium-doped aluminum nitride layer on a metal layer. They may further include etching a portion of the scandium-doped aluminum nitride layer with an etching composition. The etching composition may include greater than or about 80 wt. % phosphoric acid. The compositions may further be characterized by a temperature of greater than or about 90° C. during etching.
ACTIVELY CONTROLLED WINDOW FOR EPITAXIAL DEPOSITION PROCESS TEMPERATURE CONTROL
Granted: April 24, 2025
Application Number:
20250132175
A window component, a chamber, and a method of processing substrates are described herein. In one example, a semiconductor process chamber window component comprises a transparent quartz body. The body comprises a top surface, a bottom surface, a central portion disposed near a center axis of the body, and one or more fluid channels formed within the body. The one or more fluid channels are configured to flow a fluid from a first side of the body towards a second side of the body and the…
CHLORINE-FREE REMOVAL OF MOLYBDENUM OXIDES FROM SUBSTRATES
Granted: April 24, 2025
Application Number:
20250132165
Methods of removing molybdenum oxide from a surface of a substrate comprise exposing the substrate having a molybdenum oxide layer on the substrate to a halide etchant having the formula RmSiX4-m, wherein m is an integer from 1 to 3, X is selected from iodine (I) and bromine (Br) and R is selected from the group consisting of a methyl group, ethyl group, propyl group, butyl group, cyclohexyl group and cyclopentyl group. The methods may be performed in a back-end-of-the line (BEOL)…
MULTIZONE REFLECTOR FOR TEMPERATURE PLANAR NON-UNIFORMITY
Granted: April 24, 2025
Application Number:
20250129481
Vapor deposition processing chamber temperature control apparatus and vapor deposition processing chambers incorporating the temperature control apparatus are described. The temperature control apparatus has a base plate with a plurality of reflectors arranged in at least two annular zones, each annular zone separated into at least two sector zones. The reflectors are configured to decrease a specific side-to-side temperature non-uniformity profile of a heated substrate support…
POLISHING ARTICLES FOR HYBRID BONDING APPLICATIONS
Granted: April 17, 2025
Application Number:
20250121472
Printable resin precursor compositions and polishing articles including printable resin precursors are provided that are particularly suited for polishing substrates utilized in hybrid bonding applications. Methods and articles may include a plurality of first polishing elements, where at least one of the plurality of first polymer layers forms the polishing surface; and one or more second polishing elements, where at least a region of each of the one or more second polishing elements is…
