MULTI-THRESHOLD VOLTAGE INTEGRATION SCHEME FOR COMPLEMENTARY FIELD-EFFECT TRANSISTORS
Granted: March 13, 2025
Application Number:
20250089355
Methods of manufacturing electronic devices are described. Embodiments of the present disclosure advantageously provide methods of manufacturing electronic devices, e.g., complementary field-effect transistors (CFETs) that meet reduced thickness, reduced leakage, lower thermal budget, and Vt requirements (including multi-Vt), and have improved device performance and reliability. Some embodiments of the methods include conventional dipole engineering techniques such as dipole first…
MATERIALS AND METHODS FOR COMPLEMENTARY FIELD-EFFECT TRANSISTORS HAVING MIDDLE DIELECTRIC ISOLATION LAYER
Granted: March 13, 2025
Application Number:
20250089345
Embodiments of the disclosure advantageously provide semiconductor devices CFET in particular, and methods of manufacturing such devices having a fully strained superlattice structure with channel layers that are substantially free of defects and release layers that are protected from material loss during removal of a middle sacrificial layer. The CFET described herein comprise a vertically stacked superlattice structure on a substrate, the vertically stacked superlattice structure…
METHOD AND MATERIAL SYSTEM FOR TUNABLE HYBRID BOND INTERCONNECT RESISTANCE
Granted: March 13, 2025
Application Number:
20250087573
The interconnect resistances in a hybrid bonded structure can be controlled and designed. The resistance of each interconnect can be controlled by the width of the vias, the number of vias, and the thickness of liners within the vias. A first interconnect and a second interconnect of a hybrid bonded structure can have different interconnect resistances despite being on the same wafer or chip. The techniques described herein include designing interconnects and forming interconnects with…
SYSTEMS AND METHODS FOR SELECTIVE METAL-CONTAINING HARDMASK REMOVAL
Granted: March 13, 2025
Application Number:
20250087494
Exemplary semiconductor processing methods may include flowing an etchant precursor into a processing region of a semiconductor processing chamber. A substrate may be housed within the processing region. The substrate may define an exposed region of a metal-containing hardmask material and an exposed region of a material characterized by a dielectric constant of less than or about 4.0. The methods may include contacting the substrate with the etchant precursor. The methods may include…
METHODS OF FORMING SILICON NITRIDE FILMS
Granted: March 13, 2025
Application Number:
20250087477
Methods of depositing improved quality silicon nitride (SixNy) films are disclosed. Exemplary methods include exposing a semiconductor substrate in a semiconductor processing chamber to a silicon-containing precursor, to a first plasma produced from a first gas mixture comprising helium (He) and nitrogen (N2), the first gas mixture comprising a ratio of helium:nitrogen in a range of from 20:1 to 1000:1, and exposing the semiconductor substrate to a second plasma produced from a second…
MULTI-STAGE PUMPING LINER
Granted: March 13, 2025
Application Number:
20250087471
Exemplary semiconductor processing systems may include a pumping system, a chamber body that defines a processing region, and a pumping liner disposed within the processing region. The pumping liner may define an annular member characterized by a wall that defines an exhaust aperture coupled to the pumping system. The annular member may be characterized by an inner wall that defines a plurality of apertures distributed circumferentially along the inner wall. A plenum may be defined in…
SUPPORT UNIT
Granted: March 13, 2025
Application Number:
20250084954
A support unit for supporting a supported element, including (a) a spherical joint, (b) a pressure applying unit that is configured to maintain contact between a spherical outer surface and a base, (c) a position control unit that is configured to contact the spherical joint positioning element at multiple contact points and to set values of a first angle of rotation and a second angle of rotation of the spherical outer surface. The spherical joint is located above the position control…
MOSFET Gate Shielding Using an Angled Implant
Granted: March 6, 2025
Application Number:
20250081583
Devices and methods may include providing a device structure having a shielding layer formed beneath each trench in a MOSFET to protect trench corner breakdown. The method may include providing a device structure comprising an epitaxial layer, a well over the epitaxial layer, and a source layer over the well, and providing a plurality of trenches through the device structure. The method may further include forming a shielding layer in the device structure by directing ions into the…
METHODS OF IMPROVING PMOS TRANSISTOR PERFORMANCE
Granted: March 6, 2025
Application Number:
20250081593
Methods of manufacturing electronic devices, such as transistors (negative metal-oxide-semiconductor (NMOS) transistors (e.g., an N-metal stack) and positive metal-oxide-semiconductor (PMOS) transistors (e.g., a P-metal stack)) are described. Embodiments of the disclosure are directed to methods of improving PMOS transistor performance by inhibiting N-metal layer growth. The present disclosure provides two types of processes to reduce or inhibit N-metal layer growth. The disclosure…
CONTACT RESISTANCE REDUCTION FOR DIRECT BACKSIDE CONTACT
Granted: March 6, 2025
Application Number:
20250081592
Disclosed herein are methods for direct backside contact formation. In some embodiments, a method may include providing a stack of layers defining a front side and a backside, wherein the front side comprises one or more devices, and forming a plurality of vias in the backside, wherein each via of the plurality of vias extends to a source/drain. The method may further include performing a dopant implant to the backside including into the plurality of vias, wherein the dopant implant is…
GATE ALL AROUND 4F2 DRAM
Granted: March 6, 2025
Application Number:
20250081432
Vertical cell dynamic random-access memory (DRAM) arrays and methods of forming arrays with improved stability and word line resistivity are provided. The arrays include a plurality of bit lines arranged in a first horizontal direction and a plurality of word lines arranged in a second horizontal direction. The arrays include a plurality of channels extending in a vertical direction generally orthogonal to the first direction and the second horizontal direction, such that the plurality…
METHODS AND STRUCTURES FOR HIGH STRENGTH ASYMMETRIC DIELECTRIC IN HYBRID BONDING
Granted: March 6, 2025
Application Number:
20250079357
A first structure for semiconductor devices having a dielectric film on the top surface can be used to form semiconductor devices that are composed of hybrid bonded structures with reduced dielectric surface area and reduced pitch for metal studs. The top surface of the dielectric film of the first structure can be hybrid bonded to a dielectric layer of a second structure. The dielectric film of the first structure and the dielectric layer of the second structure can be different…
METHOD AND MATERIAL SYSTEM FOR HIGH STRENGTH SELECTIVE DIELECTRIC IN HYBRID BONDING
Granted: March 6, 2025
Application Number:
20250079356
A structure for semiconductor devices having a high-dielectric constant dielectric film on the top surface can be used to form devices that are composed of hybrid bonded structures with reduced dielectric surface area and reduced pitch for metal studs. The dielectric constant of the dielectric film can be about or greater than 8. A device can be formed by hybrid bonding the dielectric film of the structure to a dielectric film of a similar structure. A technique for forming the structure…
SECURED CRYPTO PROCESSOR FOR CHIPLET SECURITY USING ARTIFICIAL INTELLIGENCE
Granted: March 6, 2025
Application Number:
20250079342
A chiplet-based system may include a first chiplet mounted to an interposer that is designated as being from one or more trusted sources, a second chiplet mounted to the interposer that is designated as not being from the one or more trusted sources, and an artificial intelligence (AI) accelerator. The AI accelerator may be programmed to monitor a state of the first chiplet, where the state may indicate an anomaly associated with the second chiplet. The AI accelerator may then select an…
METHODS AND STRUCTURES FOR HIGH STRENGTH DIELECTRIC IN HYBRID BONDING
Granted: March 6, 2025
Application Number:
20250079312
A structure for semiconductor devices having a high-dielectric constant dielectric film on the top surface of the structure can be used to form semiconductor devices that are composed of hybrid bonded structures with reduced dielectric surface area and reduced pitch for metal studs. For example, the dielectric constant of the dielectric film can be about or greater than 7 or 8. A semiconductor device can be formed by hybrid bonding the dielectric film of the structure to a dielectric…
SUBSTRATE PRE-ALIGNER
Granted: March 6, 2025
Application Number:
20250079221
A substrate alignment system that includes (i) an illumination unit that is configured to illuminate an illuminated region that comprises an entire edge of a substrate; (ii) a sensing unit having a field of view that covers the entire edge of the substrate even when the substrate is misaligned, the sensing unit includes a sensor that is preceded by a fish eye lens, the sensor is configured to generate detection signals of the entire edge of the substrate; and (iii) a processing circuit…
ADVANCED-PACKAGING HIGH-VOLUME-MODE DIGITAL-LITHOGRAPHY-TOOL
Granted: March 6, 2025
Application Number:
20250076753
Exemplary methods of packaging a substrate may include rotationally aligning a substrate to a predetermined angular position. The methods may include transferring the substrate to a metrology station. The methods may include measuring a topology of the substrate at the metrology station. The methods may include applying a first chucking force to the substrate to flatten the substrate. The methods may include generating a mapping of a die pattern on an exposed surface of the substrate.…
METHODS OF MODIFYING OPENINGS IN HARDMASKS AND PHOTORESISTS TO ACHIEVE DESIRED CRITICAL DIMENSIONS
Granted: March 6, 2025
Application Number:
20250075315
A method of modifying an opening in a mask to achieve desired critical dimensions, the method including performing a pre-implant on the mask to implant the mask with a dopant material, wherein a material of the mask is densified and the opening is enlarged, directing a first radical beam at a first lateral side of the opening to deposit a layer of material on the first lateral side, and directing a second radical beam at a second lateral side of the opening opposite the first lateral…
GAS AMPLIFIER FOR CMP COOLING
Granted: March 6, 2025
Application Number:
20250073850
A chemical mechanical polishing chamber may include a platen disposed within the chemical mechanical polishing chamber, the platen configured to support a polishing pad. The chamber may also include a slurry delivery arm configured to deliver a slurry to the polishing pad during a chemical mechanical polishing process. The chamber may include an arm may include one or more brackets, mechanically attached to an internal side of the chemical mechanical polishing chamber and positioned over…
ROBOT BLADE AND WAFER BREAKAGE PREVENTION SYSTEM
Granted: February 27, 2025
Application Number:
20250065509
An apparatus that includes an end effector for handling and transporting wafers, the end effector including: a base portion having a first end adapted to be attached to a robot; a wafer support platform having a surface to support a wafer, a slidable joint coupling the base portion to the wafer support platform; and a sensor configured to detect when the wafer support platform slides relative to the base portion beyond a predetermined distance.
