ANNEAL CHAMBER
Granted: April 10, 2025
Application Number:
20250118572
Exemplary anneal chambers may include a base that defines a chamber interior. The base may include a cooling plate within the chamber interior. The base and the cooling plate may be integral with one another. The chambers may include a lid that is coupled with the base. The chambers may include a heater plate mounted in the chamber interior alongside the cooling plate. The chambers may include a transfer hoop movably coupled within the chamber interior. The base may define a first…
BOW MITIGATION IN HIGH ASPECT RATIO OXIDE AND NITRIDE ETCHES
Granted: April 10, 2025
Application Number:
20250118570
Methods of semiconductor processing may include forming plasma effluents. The plasma effluents may then contact a carbon-containing hardmask and an oxide cap. The plasma effluents can etch one or more features in the oxide cap through one or more apertures of the carbon-containing hardmask. Etching can create a tapered profile for one or more features in the oxide cap. The one or more features can be characterized by a critical dimension at the bottom of the one or more features. The…
CURABLE FORMULATIONS FOR POLISHING PADS
Granted: April 10, 2025
Application Number:
20250115698
Printable resin precursor compositions and polishing articles including printable resin precursors are provided. Printable resin precursors include a curable precursor formulation having a viscosity of less than or about 15 cP at 70° which include at least one urethane acrylate oligomer, at least one reactive monomer, and a photoinitiator. The curable precursor formulation exhibits an ultimate tensile strength measured in mPa and an elongation at break (%), where a product of the…
SELECTIVE ETCHING OF SILICON-AND-GERMANIUM-CONTAINING MATERIALS WITH INCREASED SURFACE PURITIES
Granted: April 3, 2025
Application Number:
20250112051
Exemplary semiconductor processing methods may include providing an oxygen-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be housed within the processing region. A first layer of silicon-and-germanium-containing material, a second layer of silicon-and-germanium-containing material, and a layer of silicon-containing material may be disposed on the substrate. The methods may include contacting the substrate with the oxygen-containing…
SEMICONDUCTOR AIRGAP SPACER AND FABRICATION METHODS
Granted: April 3, 2025
Application Number:
20250113577
Embodiments of the disclosure advantageously provide semiconductor devices, fin field effect transistors (FinFETs) in particular, and methods of manufacturing such devices having improved effective capacitance (Ceff). The FinFETs include a gate structure in which airgaps are provided by recessing a high-k material layer disposed between the gate structure and a spacer layer, thereby reducing the effective dielectric constant in the high-k dielectric layer and improving effective…
Method Of Forming A Metal Liner For Interconnect Structures
Granted: April 3, 2025
Application Number:
20250112090
Methods of forming devices comprise forming a dielectric layer on a substrate, the dielectric layer comprising at least one feature defining a gap including sidewalls and a bottom. A self-assembled monolayer (SAM) is formed on the bottom of the gap, and a barrier layer is formed on the SAM before selectively depositing a metal liner on the barrier layer. The SAM is removed after selectively depositing the metal liner on the barrier layer.
WAFER LIFT PIN GUIDE
Granted: April 3, 2025
Application Number:
20250112082
Embodiments of the present disclosure generally relate to a lift pin guide. The lift pin guide includes a cylindrical main section, a flange, a cylindrical recess, a cylindrical extension, and a bore. The flange is disposed at a first end of the cylindrical main section and has a diameter greater than a diameter of the cylindrical main section. The cylindrical recess is formed in a first surface of the flange, the first surface of the flange being opposite the cylindrical main section,…
LINE EDGE ROUGHNESS (LER) IMPROVEMENT OF RESIST PATTERNS
Granted: April 3, 2025
Application Number:
20250112056
Exemplary semiconductor processing methods may include a substrate housed in the processing region. A layer of silicon-containing material may be disposed on the substrate, a patterned resist material may be disposed on the layer of silicon-containing material, and a layer of carbon-containing material may be disposed on the patterned resist material and the layer of silicon-containing material. The methods may include providing a hydrogen-containing precursor, a nitrogen-containing…
CARBON REPLENISHMENT OF SILICON-CONTAINING MATERIALS TO REDUCE THICKNESS LOSS
Granted: April 3, 2025
Application Number:
20250112054
Exemplary methods of semiconductor processing may include providing an etchant precursor to a processing region of a semiconductor processing chamber. A structure may be disposed within the processing region. The structure may include a first silicon-containing material. The structure may include a second silicon-containing material, an oxygen-containing material, or both. The methods may include contacting the structure with the etchant precursor. The contacting with the etchant…
DIRECTIONAL RIE FEATURE RECTANGULARITY
Granted: April 3, 2025
Application Number:
20250112052
Disclosed herein are methods for forming opening ends within semiconductor structures. In some embodiments, a method may include providing an opening formed in a layer of a semiconductor device, wherein the opening comprises a set of sidewalls opposite one another, and first and second end walls connected to the sidewalls, wherein each of the first and second end walls defines a tip end and a set of curved sections extending between the tip end and the set of sidewall. The method may…
BORON CONCENTRATION TUNABILITY IN BORON-SILICON FILMS
Granted: April 3, 2025
Application Number:
20250112046
Exemplary semiconductor processing methods may include flowing a silicon-containing precursor into a substrate processing region of a semiconductor processing chamber. The methods may include flowing a boron-containing precursor into the substrate processing region of the semiconductor processing chamber. The methods may include depositing a boron-and-silicon-containing layer on a substrate in the substrate processing region of the semiconductor processing chamber. The…
LOW ENERGY TREATMENT TO PASSIVATE SiC SUBSTRATE DEFECTS
Granted: April 3, 2025
Application Number:
20250112043
Disclosed herein are methods for passivating SiC substrate defects using a low-energy treatment. In some embodiments, a method may include providing a silicon carbide (SIC) substrate, treating the SiC substrate using an ion implant or a plasma doping process, forming a first epitaxial layer over an upper surface of the SiC substrate after the SiC substrate is treated, and forming a second epitaxial layer over the first epitaxial layer.
SEAM-FREE SINGLE OPERATION AMORPHOUS SILICON GAP FILL
Granted: April 3, 2025
Application Number:
20250112039
Exemplary semiconductor processing methods may include providing a silicon-containing precursor to a processing region of a semiconductor processing chamber. A substrate including one or more features may be housed within the processing region. The methods may include providing a hydrogen-containing precursor to the processing region of the semiconductor processing chamber. The methods may include forming plasma effluents of the silicon-containing precursor and the hydrogen-containing…
METHODS FOR FORMING LOW-K DIELECTRIC MATERIALS WITH REDUCED DIELECTRIC CONSTANT AND ENHANCED ELECTRICAL PROPERTIES
Granted: April 3, 2025
Application Number:
20250112038
Exemplary semiconductor processing methods may include providing deposition precursors to a processing region of a semiconductor processing chamber. The deposition precursors may include a silicon-carbon-and-nitrogen-containing precursor. A substrate may be disposed within the processing region. The methods may include forming plasma effluents of the deposition precursors. The methods may include depositing a layer of silicon-carbon-and-nitrogen-containing material on the substrate. The…
INVERTING IMPLANTER PROCESS MODEL FOR PARAMETER GENERATION
Granted: April 3, 2025
Application Number:
20250112026
Techniques for inverting implanter process model for parameter generation are described. A method comprises receiving a set of process parameters and associated values for an ion implanter by an inverted control model, the inverted control model comprising an artificial neural network (ANN), predicting a set of control parameters and associated values for the ion implanter based on the set of process parameters and associated values by the inverted control model, and presenting the set…
CHEMICAL MECHANICAL POLISHING EDGE CONTROL WITH PAD RECESSES
Granted: April 3, 2025
Application Number:
20250108477
A Chemical Mechanical Polishing (CMP) process may generally apply more pressure around a periphery of the polishing pad than at the center of the polishing pad. This may cause uneven material removal as the substrate moves along the surface of the polishing pad. Therefore, the polishing pad may include one or more recesses around a periphery of the polishing pad to relieve pressure on the substrate. The one or more recesses may be connected to channels that extend radially outward from…
MODIFIED STACKS FOR 3D NAND
Granted: March 27, 2025
Application Number:
20250101578
Exemplary semiconductor structures may include a stack of layers overlying a substrate. The stack of layers may include a first portion of layers, a second portion of layers overlying the first portion of layers, and a third portion of layers overlying the second portion of layers. The first portion of layers, the second portion of layers, and the third portion of layers may include alternating layers of a silicon oxide material and a silicon nitride material. One or more apertures may…
DUAL WORK FUNCTION WORD LINE FOR 4F2
Granted: March 27, 2025
Application Number:
20250107068
The present technology includes vertical cell array transistor (VCAT) with improved gate induced leakage current. The arrays one or more bit lines arranged in a first horizontal direction and one or more word lines arranged in a second horizontal direction. The arrays include one or more channels extending in a vertical direction generally orthogonal to the first direction and the second horizontal direction, such that the bit lines intersect with a source/drain region of the plurality…
LOW RESISTIVITY METAL STACKS AND METHODS OF DEPOSITING THE SAME
Granted: March 27, 2025
Application Number:
20250105013
Metal stacks and methods of depositing a metal stack on a semiconductor substrate are disclosed. The metal stack is formed by depositing a tungsten (W) layer on the semiconductor substrate and depositing a molybdenum (Mo) layer on the tungsten (W) layer. The tungsten (W) layer has a thickness in a range of from 5 ? to 30 ? and the molybdenum (Mo) layer has a thickness in a range of from 80 ? to 200 ?. In some embodiments, the metal stack has a resistivity of less than or equal to 10…
RECOMBINATION CHANNELS FOR ANGLE CONTROL OF NEUTRAL REACTIVE SPECIES
Granted: March 27, 2025
Application Number:
20250104976
Provided herein are approaches for angle control of neutral reactive species ion beams. In one approach, a workpiece processing apparatus may include a plasma source operable to generate a plasma within a plasma chamber enclosed by a chamber housing, and an extraction plate coupled to the chamber housing. The extraction plate may include a recombination array having a plurality of channels operable to direct one or more radical beams to a workpiece at a non-zero angle relative to a…
