WORDLINE CONTACT FORMATION FOR NAND DEVICE
Granted: October 31, 2024
Application Number:
20240363150
Disclosed are approaches for wordline contact formation for 3D NAND devices. Methods may include providing a film stack of alternating first layers and second layers, forming a first lithography mask over the film stack, and performing a first series of alternating lithography and etch processes to form an array of contact opening pairs in the film stack, wherein an opening through the first lithography mask is expanded in a first direction following each etch process, and wherein a…
3D NAND CELLS WITH ENHANCED ERASE SPEED THROUGH DIPOLE ENGINEERING AND METHODS OF MAKING THE SAME
Granted: October 31, 2024
Application Number:
20240365551
Exemplary semiconductor structures may include a substrate. The structures may include a first layer of silicon-and-oxygen-containing material overlying the substrate. The structures may include a second layer of silicon-and-oxygen-containing material. The structures may include a first layer of metal-and-oxygen-containing material between the first layer of silicon-and-oxygen-containing material and the second layer of silicon-and-oxygen-containing material. The first layer of…
WORDLINE CONTACT FORMATION FOR NAND DEVICE
Granted: October 31, 2024
Application Number:
20240365545
Disclosed are approaches for wordline contact formation for 3D NAND devices. Methods may include providing a film stack of alternating first layers and second layers, forming a first lithography mask over the film stack, and performing a first series of alternating lithography and etch processes to form an array of contact opening pairs in the film stack, wherein an opening through the first lithography mask is expanded in a first direction following each etch process, and wherein a…
MULTI-THRESHOLD VOLTAGE INTEGRATION SCHEME FOR SEMICONDUCTOR DEVICES
Granted: October 31, 2024
Application Number:
20240363723
Methods of manufacturing electronic devices are described. Embodiments of the present disclosure advantageously provide methods of manufacturing electronic devices that meet reduced thickness, reduced leakage, lower thermal budget, and Vt requirements (including multi-Vt), and have improved device performance and reliability. The method comprises forming a P-dipole stack and an N-dipole stack on a semiconductor substrate by: depositing an interfacial layer (e.g., silicon oxide (SiOx)) on…
LOW-ENERGY UNDERLAYER FOR ROOM TEMPERATURE PHYSICAL VAPOR DEPOSITION OF ELECTRICALLY CONDUCTIVE FEATURES
Granted: October 31, 2024
Application Number:
20240363407
Embodiments of the present disclosure generally relate to a method for forming an electrically conductive feature on a substrate. In one embodiment, the method includes forming a first conductive layer via physical vapor deposition (PVD) in an opening of a substrate. The first conductive layer has a thickness of less than 20 angstroms. The method further includes forming a second conductive layer via PVD on the first conductive layer. The first conductive layer and the second conductive…
METHODS FOR BOW COMPENSATION USING TENSILE NITRIDE
Granted: October 31, 2024
Application Number:
20240363357
Embodiments of the present technology may include semiconductor processing methods. The methods may include providing deposition precursors to a processing region of a semiconductor processing chamber. The deposition precursors may include a silicon-containing precursor and a nitrogen-containing precursor. A substrate including one or more materials may be disposed within the processing region. The substrate may be characterized by a first bowing of the substrate. The methods may include…
SILICON CHANNEL FOR BONDED 3D NAND DEVICES
Granted: October 31, 2024
Application Number:
20240363345
A method for manufacturing a memory device includes depositing a seed layer in a memory hole extending through a memory stack. The seed layer includes particles, such as silicon particles. The seed layer is etched to produce etched particles. The etched particles act as nuclei for the growth of a crystalline channel material in the memory hole.
METHODS FOR FORMING LOW-K DIELECTRIC MATERIALS
Granted: October 31, 2024
Application Number:
20240363337
Semiconductor processing methods are described for forming low-? dielectric materials. The methods may include providing deposition precursors to a processing region of a semiconductor processing chamber. The deposition precursors may include a silicon-carbon-and-hydrogen-containing precursor. A substrate may be disposed within the processing region. The methods may include forming plasma effluents of the deposition precursors. The methods may include depositing a layer of…
AMORPHOUS CARBON FOR GAP FILL
Granted: October 31, 2024
Application Number:
20240363332
Methods for depositing an amorphous carbon layer on a substrate and for filling a substrate feature with an amorphous carbon gap fill are described. The method comprises performing a deposition cycle comprising: introducing a hydrocarbon source into a processing chamber; introducing a plasma initiating gas into the processing chamber; generating a plasma in the processing chamber at a temperature of greater than 600° C.; forming an amorphous carbon layer on a substrate with a deposition…
METHOD OF PLASMA CLEANING OF FUSED SILICA TUBES
Granted: October 31, 2024
Application Number:
20240363317
Methods and apparatus for cleaning a dielectric tube are described. The dielectric tube is exposed to a cleaning gas comprising a fluorine-containing compound and a microwave plasma is generated. The dielectric tube is cleaned to restore transparency and increase electronic coupling between the microwave waveguide and the plasma through the dielectric tube.
CONTROL OF LIQUID DELIVERY IN AUTO-REFILL SYSTEMS
Granted: October 31, 2024
Application Number:
20240360561
An system, method and software for controlling processes of an auto-refill system of an ampoule including one or more sensors configured to determine one or more liquid level heights within the ampoule. The auto-refill system having a state machine configured to control the auto-refill system, the state machine having one or more states for refilling the ampoule.
HALIDE AND ORGANIC PRECURSORS FOR METAL DEPOSITION
Granted: October 31, 2024
Application Number:
20240360557
Methods for depositing metal films using a metal halide and metal organic precursors are described. The substrate is exposed to a first metal precursor and a second metal precursor to form the metal film. The exposures can be sequential or simultaneous. The metal films are relatively pure with a low carbon content.
DEPOSITION APPARATUS AND METHODS USING STAGGERED PUMPING LOCATIONS
Granted: October 31, 2024
Application Number:
20240360553
Processing chambers and methods of use comprising a plurality of processing regions bounded around an outer peripheral edge by one or more vacuum channel. A first processing region has a first vacuum channel with a first outer diameter and a second processing region has a second vacuum channel with a second outer diameter, the first outer diameter being less than the second outer diameter.
SYSTEM TO COLLECT, RECOVER AND RECYCLE CHEMICAL EXHAUST FROM SEMICONDUCTOR PROCESSING CHAMBERS
Granted: October 24, 2024
Application Number:
20240350962
Chemical precursor recovery systems and methods of recovering and reusing semiconductor manufacturing chemistry are disclosed. The recovery systems include a cold trap inlet line in fluid communication with a plurality of cold traps and a cold trap outlet line. The plurality of cold traps is configured to condense the chemical precursors and are arranged based on semiconductor manufacturing process conditions.
PROCESS FOR THIN ELECTROLESS DEPOSITION
Granted: October 24, 2024
Application Number:
20240355676
A wafer-to-wafer assembly, including a first wafer having a dielectric, the dielectric having a first side and a second side, opposite the first side, at least one opening etched into first side of the dielectric, a plug seed layer disposed on the first side of the dielectric, a plug disposed in the at least one opening, a first thin layer deposited over the plug, and a second thin layer deposited over the first thin layer. The first thin layer, the second thin layer, or both the first…
METHODS OF FORMING INTERCONNECT STRUCTURES
Granted: October 24, 2024
Application Number:
20240355675
Methods of forming semiconductor devices by enhancing selective deposition are described. In some embodiments, a blocking layer is deposited on a metal surface before deposition of a barrier layer. The methods include exposing a substrate with a metal surface, a dielectric surface and an aluminum oxide surface or an aluminum nitride surface to a blocking molecule, such as a boron-containing compound, to form the blocking layer selectively on the metal surface over the dielectric surface…
NANOCRYSTALLINE DIAMOND WITH AMORPHOUS INTERFACIAL LAYER
Granted: October 24, 2024
Application Number:
20240352621
Methods of depositing a nanocrystalline diamond film are described. The method may be used in the manufacture of integrated circuits. Methods include treating a substrate with a plasma to form a treated substrate surface, incubating the treated substrate with a carbon-rich plasma to nucleate diamond particles on the treated substrate surface, followed by treating the substrate with a plasma to form a nanocrystalline diamond film. The resulting nanocrystalline diamond films are formed on…
DITHERING OR DYNAMIC OFFSETS FOR IMPROVED UNIFORMITY
Granted: October 24, 2024
Application Number:
20240352586
Apparatus and methods to process one or more substrates are described. A plurality of process stations are arranged in a circular configuration around a rotational axis. A support assembly with a rotatable center base defining a rotational axis, at least two support arms extending from the center base and heaters on each of the support arms is positioned adjacent the processing stations so that the heaters can be moved amongst the various process stations to perform one or more process…
SIDE PUMPING CHAMBER AND DOWNSTREAM RESIDUE MANAGEMENT HARDWARE
Granted: October 24, 2024
Application Number:
20240352580
Exemplary semiconductor processing chambers may include a chamber body having sidewalls and a base. The chambers may include a pumping liner seated atop the chamber body. The pumping liner may at least partially define an annular pumping plenum and at least one exhaust aperture that fluidly couples the pumping plenum with an interior of the chamber body. The chambers may include a purge ring seated below the pumping liner. The purge ring may define an annular channel that extends about a…
PLASMA BASED FILM MODIFICATION FOR SEMICONDUCTOR DEVICES
Granted: October 24, 2024
Application Number:
20240352575
Disclosed herein are approaches for treating a film layer of a semiconductor device to modify an etch resistance of the film later. In one approach, a method may include forming a first film over a substrate base, depositing a second film over the first film, and introducing an inert species into the second film while the second film is deposited over the first film, wherein the inert species increases an etch-resistance of a first portion of the first film. The method may further…
