CONDUCTIVE OXIDE SILICIDES FOR RELIABLE LOW CONTACT RESISTANCE
Granted: August 24, 2023
Application Number:
20230268415
Embodiments of the disclosure provide methods and electronic devices comprising a work function layer comprising a material that forms a conductive oxide with or without titanium. The electronic devices comprise a silicon layer with the work function layer thereon and a metal contact on the work function layer.
SILICIDES, ALLOYS AND INTERMETALLICS TO MINIMIZE RESISTANCE
Granted: August 24, 2023
Application Number:
20230268414
Embodiments of the disclosure provide methods and electronic devices comprising a work function layer comprising a material that forms a weak silicide. The electronic devices comprise a silicon layer with the work function layer thereon and a metal contact on the work function layer.
SIMULATION OF ATOMISTIC DEFECTS IN NANOELECTRONICS USING POLYHEDRAL MESHES
Granted: August 17, 2023
Application Number:
20230259687
A simulation of an electronic device may use a distribution of atomistic defects to provide more accurate results. An input mesh may be received representing a physical structure of the electronic device. This input mesh may be transformed into a polyhedral mesh to facilitate the simulation. A distribution of defects may then be generated and distributed throughout the polyhedral mesh. When performing each time step of the simulation, the effects of these defects may be attributed to…
HIGH QUALITY QUANTUM COMPUTER COMPONENTS
Granted: August 17, 2023
Application Number:
20230263075
Exemplary methods of fabricating high quality quantum computing components are described. The methods include removing native oxide from a deposition surface of a silicon substrate in a cleaning chamber of a processing system, and transferring the silicon substrate under vacuum to a deposition chamber of the processing system. The methods further include depositing an aluminum layer on the deposition surface of the silicon substrate in the deposition chamber, where an interface between…
TUNABLE INTEGRATED VOLTAGE REGULATOR
Granted: August 17, 2023
Application Number:
20230261570
An integrated voltage regulator (IVR) for on-chip integrated circuit applications may include a tunable inductor that may be adjusted to generate a target output for the IVR. The tunable inductor may include a piezoelectric material that may cause the relative permeability of the inductor to change based on an applied stimulus voltage. A control circuit may receive a target value, such as a target output voltage, and retrieve or calculate a target inductance value or voltage to be…
GATE ALL AROUND BACKSIDE POWER RAIL WITH DIFFUSION BREAK
Granted: August 17, 2023
Application Number:
20230260909
Semiconductor devices and methods of manufacturing the same are described. The method includes forming a diffusion break opening on the backside and filling with a diffusion break material to serve as a planarization stop. In some embodiments, a single diffusion break opening is formed. In other embodiments, a mixed diffusion break opening is formed.
GATE ALL AROUND BACKSIDE POWER RAIL FORMATION WITH MULTI-COLOR BACKSIDE DIELECTRIC ISOLATION SCHEME
Granted: August 17, 2023
Application Number:
20230260908
Semiconductor devices and methods of manufacturing the same are described. The method includes forming distinct and separate bottom dielectric isolation layers underneath the source/drain and underneath the gate of a gate all around device. Selectively remove of the bottom dielectric isolation layer underneath the source/drain results in better backside power rail (BPR) via alignment to the source/drain epi and reduces reliability and gate-shorting problems.
HIGHLY SELECTIVE SILICON ETCHING
Granted: August 17, 2023
Application Number:
20230260802
Exemplary semiconductor processing methods may include providing a fluorine-containing precursor and a hydrogen-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region of the semiconductor processing chamber. The substrate may include at least one layer of silicon-containing material and at least one layer of silicon-and-germanium-containing material along the substrate. The methods may include forming a…
METHODS TO REDUCE UNCD FILM ROUGHNESS
Granted: August 17, 2023
Application Number:
20230260800
Hard masks and methods of forming hard masks are described. The hard mask has an average roughness less than 10 nm and a modulus greater than or equal to 400 GPa. The method comprises exposing a substrate to a deposition gas comprising a dopant gas or a precursor (solid (e.g. Alkylborane compounds) or liquid (e.g. Borazine)), a carbon gas and argon at a temperature less than or equal to 550 C, and igniting a plasma from the deposition gas to form an ultrananocrystalline diamond film…
INTEGRATED DIPOLE REGION FOR TRANSISTOR
Granted: August 17, 2023
Application Number:
20230260791
Methods of manufacturing and processing semiconductor devices (i.e., electronic devices) are described. Embodiments of the disclosure advantageously provide electronic devices which comprise an integrated dipole region to meet reduced thickness and lower thermal budget requirements. The electronic devices described herein comprise a source region, a drain region, and a channel separating the source region and the drain region, and a dipole region having an interfacial layer, a metal film…
PARAMETER ADJUSTMENT MODEL FOR SEMICONDUCTOR PROCESSING CHAMBERS
Granted: August 17, 2023
Application Number:
20230257900
A system may include a first semiconductor processing station configured to deposit a material on a first semiconductor wafer, a second semiconductor processing station configured perform measurements indicative of a thickness of the material after the material has been deposited on the first semiconductor wafer, and a controller. The controller may be configured to receive the measurements from the second station; provide an input based on the measurements to a trained model that is…
HIGH ASPECT RATIO TAPER IMPROVEMENT USING DIRECTIONAL DEPOSITION
Granted: August 17, 2023
Application Number:
20230257872
Disclosed are approaches for forming semiconductor device cavities. One method may include providing a set of semiconductor structures defining an opening, wherein the opening has a first opening width along an upper portion of the opening and a second opening width along a lower portion of the opening, the first opening width being greater than the second opening width. The method may further include forming a blocking layer along the set of semiconductor structures by delivering a…
P-TYPE DIPOLE FOR P-FET
Granted: August 10, 2023
Application Number:
20230253466
Methods of forming and processing semiconductor devices are described. Certain embodiments related to electronic devices which comprise a dipole region having an interlayer dielectric, a high-? dielectric material, and a dipole layer. The dipole layer comprises one or more of titanium aluminum nitride (TiAIN), titanium tantalum nitride (TiTaN), titanium oxide (TiO), tantalum oxide (TaO), and titanium aluminum carbide (TiAIC).
METHODS OF FORMING METAL LINER FOR INTERCONNECT STRUCTURES
Granted: August 10, 2023
Application Number:
20230253248
Methods of forming devices comprise forming a dielectric layer on a substrate, the dielectric layer comprising at least one feature defining a gap including sidewalls and a bottom. The methods include selectively depositing a self-assembled monolayer (SAM) on the bottom of the gap. The SAM comprises a hydrocarbon having a formula of H—C?C—R, wherein R is a linear alkyl chain or aryl group comprising from 1 to 20 carbon atoms or a formula of R?C?CR?, wherein R? and R? independently…
ION IMPLANTATION TO CONTROL BURIED CHANNEL RECESS DEPTH
Granted: August 10, 2023
Application Number:
20230253208
Disclosed herein are approaches for reducing buried channel recess depth using a non-doping ion implant prior to formation of the buried channel. In one approach, a method may include providing an oxide layer over a substrate, performing a non-doping implantation process through the oxide layer to form an amorphous region in the substrate, and forming a photoresist over the oxide layer. The method may further include forming a buried layer in the substrate by implanting the substrate…
CHALCOGEN PRECURSORS FOR DEPOSITION OF SILICON NITRIDE
Granted: August 10, 2023
Application Number:
20230253201
Chalcogen silane precursors are described. Methods for depositing a silicon nitride (SixNy) film on a substrate are described. The substrate is exposed to the chalcogen silane and a reactant to deposit the silicon nitride (SixNy) film. The exposures can be sequential or simultaneous. The chalcogen silane may be substantially free of halogen. The chalcogen may be selected from the group consisting of sulfur (S), selenium (Se), and tellurium (Te).
PEALD TITANIUM NITRIDE WITH DIRECT MICROWAVE PLASMA
Granted: August 10, 2023
Application Number:
20230253186
A method of depositing titanium nitride is disclosed. Some embodiments of the disclosure provide a PEALD process for depositing titanium nitride which utilizes a direct microwave plasma. In some embodiments, the direct microwave plasma has a high plasma density and low ion energy. In some embodiments, the plasma is generated directly above the substrate surface.
SIDEWALL PASSIVATION FOR PLASMA ETCHING
Granted: August 3, 2023
Application Number:
20230245895
Exemplary semiconductor processing methods may include depositing a boron-containing material on the substrate. The boron-containing material may extend along sidewalls of the one or more features in the substrate. The methods may include forming a plasma of an oxygen-containing precursor and contacting the substrate with plasma effluents of the oxygen-containing precursor. The contacting may etch a portion of the one or more features in the substrate. The contacting may oxidize the…
WAFER IMMERSION IN SEMICONDUCTOR PROCESSING CHAMBERS
Granted: August 3, 2023
Application Number:
20230243059
A semiconductor processing chamber may process wafers by submerging the wafers in a liquid. To determine when the liquid is free of disturbances or contaminants and thus ready to receive the next wafer, a camera may be positioned to capture images of the liquid after a wafer has been removed from the liquid. A controller may provide the images of the liquid to a neural network to determine when the liquid is ready based on an output of the neural network. The neural network may be…
PLASMA SOURCE FOR SEMICONDUCTOR PROCESSING
Granted: July 27, 2023
Application Number:
20230238221
The present technology encompasses plasma sources including a first plate defining a first plurality of apertures arranged in a first set of rows. The first plate may include a first set of electrodes extending along a separate row of the first set of rows. The plasma sources may include a second plate defining a second plurality of apertures arranged in a second set of rows. The second plate may include a second set of electrodes extending along a separate row of the second set of rows.…
