DIRECT WORD LINE CONTACT AND METHODS OF MANUFACTURE FOR 3D MEMORY
Granted: November 16, 2023
Application Number:
20230371246
Described are memory devices having an array region and an extension region adjacent the array region. The array region includes at least two unit cells stacked vertically. The extension region includes a memory stack and a plurality of word line contacts. The memory stack comprises alternating layers of at least one conductive layer, a semiconductor layer, and an insulating layer. The plurality of word line contacts extend through the memory stack to the at least one conductive layer.…
STRESS RELAXATION TRENCHES FOR GALLIUM NITRIDE MICROLED LAYERS ON SILICON SUBSTRATES
Granted: November 16, 2023
Application Number:
20230369532
A microLED-quality layer of gallium nitride (GaN) may be formed above a silicon substrate for microLED devices to be formed. Typically, mismatches between the crystal lattice of the GaN and the silicon substrate cause internal stresses that bow the wafer. To relieve these stresses, a pattern of trenches may be etched into the GaN layer between the die or device footprints. These trenches may be etched through the GaN layer, down to the depth of the silicon substrate, or even down into…
THREE DIMENSIONAL DEVICE FORMATION USING EARLY REMOVAL OF SACRIFICIAL HETEROSTRUCTURE LAYER
Granted: November 16, 2023
Application Number:
20230369453
A method for forming a nanosheet device. The method may include providing a heterostructure device stack above a semiconductor substrate. The method may include patterning the heterostructure device stack to define a dummy gate region, and before forming a source drain recess adjacent the dummy gate region, selectively removing a first set of sacrificial layers of the heterostructure device stack within the dummy gate region.
METHODS FOR FORMING MULTI-TIER TUNGSTEN FEATURES
Granted: November 16, 2023
Application Number:
20230369113
A method of forming a structure on a substrate includes forming a tungsten nucleation layer within at least one opening within a multi-tier portion of a substrate. The method includes exposing the nucleation layer a nitrogen trifluoride-containing gas to inhibit growth of the nucleation layer at narrow portions within the at least one opening. The method includes exposing the at least one opening to the tungsten-containing precursor gas to form a fill layer over the nucleation layer…
TECHNIQUES FOR VOID-FREE MATERIAL DEPOSITIONS
Granted: November 16, 2023
Application Number:
20230369112
Embodiments herein include void-free material depositions on a substrate (e.g., in a void-free trench-filled (VFTF) component) obtained using directional etching to remove predetermined portions of a seed layer covering the substrate. In several embodiments, directional etching followed by selective deposition can enable fill material (e.g., metal) patterning in tight spaces without any voids or seams. Void-free material depositions may be used in a variety of semiconductor devices, such…
SYSTEMS AND METHODS TO REDUCE FLOW ACCURACY ERROR FOR LIQUID & GAS MASS FLOW CONTROLLER DEVICES
Granted: November 16, 2023
Application Number:
20230369072
Exemplary fluid delivery assemblies for a semiconductor processing system may include a liquid delivery source. The assemblies may include a heater that is fluidly coupled with an outlet of the liquid delivery source. The assemblies may include a liquid flow controller that is fluidly coupled with the liquid delivery source downstream of the heater. The assemblies may include a liquid vaporizer fluidly coupled with a downstream end of the liquid flow controller. The assemblies may…
Etch Rate Modulation of FinFET Through High-Temperature Ion Implantation
Granted: November 16, 2023
Application Number:
20230369050
A method of forming a semiconductor device may include forming a plurality of fins extending from a buried oxide layer, wherein a masking layer is disposed atop each of the plurality of fins, and performing a high-temperature ion implant to the semiconductor device. The method may further include performing an etch process to remove the masking layer from atop each of the plurality of fins, wherein the etch process does not remove the buried oxide layer.
INTEGRATED METHOD AND TOOL FOR HIGH QUALITY SELECTIVE SILICON NITRIDE DEPOSITION
Granted: November 16, 2023
Application Number:
20230369031
Methods of manufacturing memory devices are provided. The method comprises pre-cleaning a top surface of a film stack, the film stack comprising alternating layers of a first material layer and a second material layer and having one or more of a memory hole and a slit pattern opening extending through the film stack; exposing the top surface of the film stack to a growth inhibitor; selectively depositing a silicon-containing dielectric layer in a region of the film stack; and densifying…
RECOMBINATION CHANNELS FOR ANGLE CONTROL OF NEUTRAL REACTIVE SPECIES
Granted: November 16, 2023
Application Number:
20230369022
Provided herein are approaches for angle control of neutral reactive species ion beams. In one approach, a workpiece processing apparatus may include a plasma source operable to generate a plasma within a plasma chamber enclosed by a chamber housing, and an extraction plate coupled to the chamber housing. The extraction plate may include a recombination array having a plurality of channels operable to direct one or more radical beams to a workpiece at a non-zero angle relative to a…
DRY TREATMENT FOR SURFACE LOSS REMOVAL IN MICRO-LED STRUCTURES
Granted: November 9, 2023
Application Number:
20230361242
A mesa etch may form the geometry of microLED structures. However, the mesa etch may induce defects in the microLED structures that decreases the efficiency of the microLEDs. To correct these defects, a dry etch process may be performed that incrementally removes the surface layers of the microLED structures with the defects. The dry etch may be configured to incrementally remove a small outer layer, and thus may preserve the overall shape of the microLED structures while leaving a…
CONFORMAL METAL DICHALCOGENIDES
Granted: November 9, 2023
Application Number:
20230360967
Transition metal dichalcogenide films and methods for depositing transition metal dichalcogenide films on a substrate are described. Methods for converting transition metal oxide films to transition metal dichalcogenide films are also described. The substrate is exposed to a metal precursor and an oxidant to form a transition metal oxide film; the transition metal oxide film is exposed to a chalcogenide precursor to form the transition metal dichalcogenide film.
WAFER FILM FRAME CARRIER
Granted: November 9, 2023
Application Number:
20230360940
Exemplary semiconductor substrate carrier frames may include a frame body defining a central aperture. The frames may include a plurality of fingers that are coupled with the frame body. Each of the plurality of fingers may extend into the central aperture. Each of the plurality of fingers may include a substrate receiving interface. At least one of the plurality of fingers may include an actuator that manipulates a respective one of the at least one of the plurality of fingers between a…
LOW TEMPERATURE CARBON GAPFILL
Granted: November 9, 2023
Application Number:
20230360924
Exemplary methods of semiconductor processing may include providing a carbon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region of the semiconductor processing chamber. The substrate may define one or more features along the substrate. The methods may include forming a plasma of the carbon-containing precursor within the processing region. The methods may include depositing a carbon-containing…
SILICON-AND-CARBON-CONTAINING MATERIALS WITH LOW DIELECTRIC CONSTANTS
Granted: November 9, 2023
Application Number:
20230360906
Exemplary methods of semiconductor processing may include providing a silicon-containing precursor and a carbon-containing precursor to a processing region of a semiconductor processing chamber. The carbon-containing precursor may be characterized by a carbon-carbon double bond or a carbon-carbon triple bond. A substrate may be disposed within the processing region of the semiconductor processing chamber. The methods may include providing an oxygen-containing precursor to the processing…
LARGE AREA GAPFILL USING VOLUMETRIC EXPANSION
Granted: November 9, 2023
Application Number:
20230360903
Exemplary methods of semiconductor processing may include providing a silicon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region of the semiconductor processing chamber. The substrate may define one or more features along the substrate. The methods may include depositing a silicon-containing material on the substrate. The silicon-containing material may extend within the one or more features along…
ALD CYCLE TIME REDUCTION USING PROCESS CHAMBER LID WITH TUNABLE PUMPING
Granted: November 9, 2023
Application Number:
20230357927
Process chamber lids having a pumping liner with a showerhead and gas funnel within an open central region are described. The showerhead is spaced a distance from the gas funnel to form a gap and the gas funnel has an opening to provide a flow of gas into the gap. The gas funnel includes a plurality of apertures extending from the front surface to a common region adjacent the back surface of the gas funnel. A purge ring is in contact with the back surface of the gas funnel and aligned so…
POLISHING HEAD WITH LOCAL INNER RING DOWNFORCE CONTROL
Granted: November 9, 2023
Application Number:
20230356355
Exemplary carrier heads for a chemical mechanical polishing apparatus may include a carrier body. The carrier heads may include a substrate mounting surface coupled with the carrier body. The carrier heads may include an inner ring that is sized and shaped to circumferentially surround a peripheral edge of a substrate positioned against the substrate mounting surface. The inner ring may be characterized by a first surface that faces the carrier body and a second surface opposite the…
COMPLIANT INNER RING FOR A CHEMICAL MECHANICAL POLISHING SYSTEM
Granted: November 9, 2023
Application Number:
20230356354
Exemplary carrier heads for a chemical mechanical polishing apparatus may include a carrier body. The carrier heads may include a substrate mounting surface coupled with the carrier body. The carrier heads may include an inner ring that is sized and shaped to circumferentially surround a peripheral edge of a substrate positioned against the substrate mounting surface. The inner ring may be characterized by a first end having a first surface that faces the carrier body and a second end…
PHOTOLUMINESCENT MATERIALS WITH PHOSPHOROUS ADDITIVES TO REDUCE PHOTODEGRADATION
Granted: November 2, 2023
Application Number:
20230348778
Multilayered semiconductor particles, which may be referred to as a quantum dots, may include a zinc-containing core. The particles may include a zinc-and-selenium-containing inner shell on the zinc-containing core. The particles may include a zinc-containing outer shell on the zinc-and-selenium-containing inner shell. The particles may include a phosphorous-containing material in contact with the zinc-containing outer shell. The phosphorous-containing material may be or include…
PLATING SYSTEMS HAVING REDUCED AIR ENTRAINMENT
Granted: November 2, 2023
Application Number:
20230349064
Electroplating processing systems according to the present technology may include a recirculating tank containing a first volume of processing fluid. The recirculating tank may be fluidly coupled with a delivery pump. The systems may include a vessel configured to receive the processing fluid from the pump. The vessel may include an inner chamber and an outer chamber, and the inner chamber may be sized to hold a second volume of processing fluid less than the first volume of processing…
