VIRTUAL APPLIANCE ON A CHIP
Granted: April 6, 2017
Application Number:
20170097838
Various embodiments provide for a system that integrates 64 bit ARM cores and a switch on a single chip. The RISC style processors use highly optimized sets of instructions rather than the specialized set of instructions found in other architectures (e.g., x86). The system also includes multiple high bandwidth ports that enable multi-ported virtual appliances to be built using a single chip. The virtual appliances are software implemented versions of the physical appliances that are…
SYSTEM AND METHOD FOR MONITORING ENCODED SIGNALS IN A NETWORK
Granted: January 21, 2016
Application Number:
20160020978
Various aspects provide for non-intrusively monitoring a network system. A multiplexing component is configured to receive a plurality of first encoded signals and generate a plurality of second encoded signals. The plurality of second encoded signals contain a different data rate and a different number of network lanes than the plurality of first encoded signals. A monitoring component is configured to identify a block location for repeating blocks and an alignment marker in each of the…
DUPLEX TRANSMISSION OVER REDUCED PAIRS OF TWINAX CABLES
Granted: November 12, 2015
Application Number:
20150326379
Cable systems and assemblies integrate a reduced number of twin axial copper pairs to transmit and received in a full-duplex transmission signals at transmission speeds greater than or equal to one hundred Giga bytes per second. The reduced number of twin axial copper pairs comprise four or less twin axial copper pairs, in which each pair forms a single twin axial full-duplex cable for passive or active communication of the signals. A processor can be integrated with the twin axial…
PROGRAMMABLE GAIN AMPLIFIER WITH CONTROLLED GAIN STEPS
Granted: November 12, 2015
Application Number:
20150326197
Provided is a programmable gain amplifier that includes controlled gain steps that dynamically control an output voltage in real-time. The programmable gain amplifier includes a first transistor and a second transistor that includes respective control ports, input ports, and output ports. The programmable gain amplifier also includes a resistor connected to the output ports of the transistors. Further, at least a third transistor is connected to the output ports, in parallel with the…
FLOW PINNING IN A SERVER ON A CHIP
Granted: November 12, 2015
Application Number:
20150324306
Various embodiments provide for a system on a chip or a server on a chip that performs flow pinning, where packets or streams of packets are enqueued to specific queues, wherein each queue is associated with a respective core in a multiprocessor/multi-core system or server on a chip. With each stream of packets, or flow, assigned to a particular processor, the server on a chip can process and intake packets from multiple queues from multiple streams from the same single Ethernet…
HAZARD PREDICTION FOR A GROUP OF MEMORY ACCESS INSTRUCTIONS USING A BUFFER ASSOCIATED WITH BRANCH PREDICTION
Granted: November 12, 2015
Application Number:
20150324203
Various aspects provide for facilitating prediction of instruction pipeline hazards in a processor system. A system comprises a fetch component and an execution component. The fetch component is configured for storing a hazard prediction associated with a group of memory access instructions in a buffer associated with branch prediction. The execution component is configured for executing a memory access instruction associated with the group of memory access instructions as a function of…
SYSTEMS AND METHODS FACILITATING MULTI-WORD ATOMIC OPERATION SUPPORT FOR SYSTEM ON CHIP ENVIRONMENTS
Granted: November 12, 2015
Application Number:
20150324133
Systems and methods that facilitate multi-word atomic operation support for systems on chip are described. One method involves: receiving an instruction associated with a calling process, and determining a first memory width associated with execution of the instruction based on an operator of the instruction and a width of at least one operand of the instruction. The instruction can be associated with an atomic operation. In some embodiments, the instruction contains a message having a…
GENERATING A TIMEOUT SIGNAL BASED ON A CLOCK COUNTER ASSOCIATED WITH A DATA REQUEST
Granted: November 12, 2015
Application Number:
20150323956
Various aspects provide for generating a timeout signal based on a clock counter associated with a data request. An interface component is configured for receiving a data request from a master device and forwarding the data request to a slave device. A timeout component is configured for maintaining a clock counter associated with the data request and generating a timeout signal in response to a determination that a threshold level associated with the clock counter is reached before…
HIGH FREQUENCY VOLTAGE SUPPLY MONITOR
Granted: November 12, 2015
Application Number:
20150323569
Various aspects provide a high frequency voltage supply monitor capable of monitoring high frequency variations of the voltage supply inside a microelectronic circuit substantially in real time. The voltage supply monitor can comprise a differential amplifier circuit having a substantially constant gain over a wide bandwidth, allowing the supply voltage variations to be amplified according to a known gain under a wide range of conditions. The amplified signal can then be sent to an…
IMPLEMENTATION OF LOAD ACQUIRE/STORE RELEASE INSTRUCTIONS USING LOAD/STORE OPERATION WITH DMB OPERATION
Granted: November 5, 2015
Application Number:
20150317158
A system and method are provided for simplifying load acquire and store release semantics that are used in reduced instruction set computing (RISC). Translating the semantics into micro-operations, or low-level instructions used to implement complex machine instructions, can avoid having to implement complicated new memory operations. Using one or more data memory barrier operations in conjunction with load and store operations can provide sufficient ordering as a data memory barrier…
TIMES-SLICED DESIGN SEGMENTATION
Granted: June 11, 2015
Application Number:
20150163024
Systems and methods for multi-channel signal processing by a series of single processing core logic circuitries in time-slicing. A first logic circuitry is configured to process multiple data streams from multiple channels in a first cycle-based time-sliced schedule. A time slice in the first cycle-based time-sliced schedule comprises a predetermined number of clock cycles allocated to a corresponding data stream. A second logic circuitry is coupled to the first logic circuitry and…
ALLOCATION OF LOAD INSTRUCTION(S) TO A QUEUE BUFFER IN A PROCESSOR SYSTEM BASED ON PREDICTION OF AN INSTRUCTION PIPELINE HAZARD
Granted: June 11, 2015
Application Number:
20150160945
Various aspects provide for detecting ordering violations in a memory system. A system includes a prediction component and an execution component. The prediction component predicts whether a load instruction in the system is associated with an instruction pipeline hazard. The execution component allocates the load instruction to a queue buffer in the system in response to a prediction that the load instruction is not associated with the instruction pipeline hazard.
MULTPLE DATASTREAMS PROCESSING BY FRAGMENT-BASED TIMESLICING
Granted: May 28, 2015
Application Number:
20150150009
Systems and methods for multi-channel signal processing by virtue of packet-based time-slicing with single processing core logic. The processing core logic is configured to receive data streams from the multiple communication channels at a data processing unit, and process data fragments of the data streams in a time-sliced manner. The processing core logic can switch from processing a first data fragment of a first data stream to processing a first data fragment of a second data stream…
JITTER MITIGATING PHASE LOCKED LOOP CIRCUIT
Granted: April 23, 2015
Application Number:
20150110233
Systems and methods for efficient jitter mitigation or removal from a gapped signal. A phase mitigation module is employed to generate discrete correction values for modifying phase error signals detected between a gapped signal and a feedback signal of the PLL. The correction values can be digitally subtracted from the output of a phase frequency detector associated with the PLL. The sequence of correction values can be determined based on phase frequency differences between the input…
DEFECT PROPAGATION OF MULTIPLE SIGNALS OF VARIOUS RATES WHEN MAPPED INTO A COMBINED SIGNAL
Granted: April 16, 2015
Application Number:
20150106679
Systems and methods for detecting defect propagation in a networked environment comprising a defect detection component to detect defects in an aggregate signal and/or in individual signals; and a replacement signal component to generate a maintenance signal to replace defective signals detected by the defect detection component. The maintenance signal can be a uniform signal type regardless of a type associated with a defective signal. The maintenance signal can replace a defective…
TCP SEGMENTATION OFFLOAD IN A SERVER ON A CHIP
Granted: April 9, 2015
Application Number:
20150098469
A system and method are provided for performing transmission control protocol segmentation on a server on a chip using coprocessors on the server chip. A system processor manages the TCP/IP stack and prepares a large (64 KB) single chunk of data to be sent out via a network interface on the server on a chip. The system software processes this and calls the interface device driver to send the packet out. The device driver, instead of sending the packet out directly on the interface, calls…
MULTI-STAGE ADDRESS TRANSLATION FOR A COMPUTING DEVICE
Granted: April 2, 2015
Application Number:
20150095610
Providing for address translation in a virtualized system environment is disclosed herein. By way of example, a memory management apparatus is provided that comprises a shared translation look-aside buffer (TLB) that includes a plurality of translation types, each supporting a plurality of page sizes, one or more processors, and a memory management controller configured to work with the one or more processors. The memory management controller includes logic configured for caching virtual…
MAPPING A PLURALITY OF SIGNALS TO GENERATE A COMBINED SIGNAL COMPRISING A HIGHER DATA RATE THAN A DATA RATE ASSOCIATED WITH THE PLURALITY OF SIGNALS
Granted: March 19, 2015
Application Number:
20150078406
Various aspects provide for mapping a plurality of signals to generate a combined signal. An aggregation component is configured for generating a combined signal that comprises a higher data rate than a data rate associated with a plurality of signals based on mapped data associated with the plurality of signals. The aggregation component comprises a mapper component. The mapper component is configured for generating the mapped data based on a mapping distribution pattern associated with…
REFORMATING A PLURALITY OF SIGNALS TO GENERATE A COMBINED SIGNAL COMPRISING A HIGHER DATA RATE THAN A DATA RATE ASSOCIATED WITH THE PLURALITY OF SIGNALS
Granted: March 12, 2015
Application Number:
20150071311
Various aspects provide for aggregating a plurality of signals to generate a combined signal. An aggregation component is configured for reformatting a plurality of first signals and combining the plurality of first signals to generate a combined signal that comprises a higher data rate than a data rate associated with the plurality of first signals. A transmitter component is configured for receiving the combined signal and generating one or more data streams based on the combined…
DISCRETE TIME COMPENSATION MECHANISMS
Granted: March 5, 2015
Application Number:
20150067381
Discrete time compensation mechanisms include a channel component configured for determining which channel of a plurality of channels to process time slots of sampled data that are time stamped in a discrete time and processing the time slots of the sampled data to the plurality of channels. A common channel clock component is configured for time stamping the time slots of the sampled data in the discrete time domain that is faster than a non-discrete reference time stamp of continuous…
