RETRIEVAL HASH INDEX
Granted: February 19, 2015
Application Number:
20150052286
Systems and methods are provided that facilitate retrieval of a hash index in an electronic device. The system contains an addressing component that generates a hash index as a function of an exclusive-or identity. The addressing component can retrieve the hash index as a function of a tag value. Accordingly, required storage area can be reduced and electronic devices can be more efficient.
FAST FILTERING FOR A TRANSCEIVER
Granted: February 19, 2015
Application Number:
20150049847
Techniques for fast filtering for a transceiver are presented. A multidimensional filter processor component (MDFPC) can perform configurations and adaptations of multiple digital filters of a transceiver. The MDFPC can treat multiple, separate filters of a transceiver as a single larger multidimensional filter, and jointly update the multiple filters in a single adaptation operation instead of performing multiple adaptation operations on multiple filters. To facilitate multidimensional…
END-TO-END FLOW CONTROL IN SYSTEM ON CHIP INTERCONNECTS
Granted: January 29, 2015
Application Number:
20150032794
Provided is an end-to-end flow control management for a system on chip interface. As tokens are injected into agents arranged in a computer network, the input point for the token is dynamically changed such that tokens are not always injected into the same agent. Additionally or alternatively, as tokens are injected into a token ring, the tokens are initially not activated until a predetermined event occurs (e.g., after a specific number of hops). Additionally or alternatively, also…
DYNAMIC POWER CONTROL
Granted: September 25, 2014
Application Number:
20140289541
Systems and methods are provided that facilitate power management in a processing device. The system contains a power management component and a coupled to the processing device. The power management component determines and input rate and target voltages and/or frequency. The power management component can scale voltages and/or frequencies based on target voltages and/or frequencies. Accordingly, power consumption can be reduced and processing devices can be more efficient.
CACHE MISS DETECTION FILTER
Granted: September 25, 2014
Application Number:
20140289467
Systems and methods are provided that facilitate cache miss detection in an electronic device. The system contains a probabilistic filter coupled to the processing device. A probing component determines existence of an entry associated with a request. The probing component can communicate a miss token without the need to query a cache. Accordingly, power consumption can be reduced and electronic devices can be more efficient.
FREQUENCY SYNTHESIS WITH GAPPER
Granted: September 18, 2014
Application Number:
20140266328
Systems and methods for frequency synthesis using a gapper. A frequency synthesizer may comprise a gapper, a first integer divider and a Phase Locked Loop (PLL). When a frequency of an output signal is intended to be greater than a corresponding input signal, a factor can be borrowed by the gapper from the first integer divider to generate a rational divide ratio G that is greater 1 in order for the gapper to be capable of performing the division by G. The PLL is capable of multiplying a…
DEBUGGING PROCESSOR HANG SITUATIONS USING AN EXTERNAL PIN
Granted: September 18, 2014
Application Number:
20140281722
Various aspects provide forced halt functionality for a processor to facilitate troubleshooting of processor hang situations. In the event that the processor initiates a transaction that does not receive a completion acknowledgement, a forced halt sequence can be initiated, which causes the processor to abort all pending transactions and transition to a debug state so that the internal state of the processor can be viewed. In addition, the processor can maintain a record of the processor…
PROCESSOR HANG DETECTION AND RECOVERY
Granted: September 18, 2014
Application Number:
20140281695
Various aspects provide forced halt functionality for a processor to facilitate troubleshooting of processor hang situations. In the event that the processor initiates a transaction that does not receive a completion acknowledgement, halt detection logic can initiate a forced halt sequence that causes the processor to abort all pending transactions and transition to a debug state so that the internal state of the processor can be viewed. In addition, the processor can maintain a record…
BROADCAST MESSAGING AND ACKNOWLEDGMENT MESSAGING FOR POWER MANAGEMENT IN A MULTIPROCESSOR SYSTEM
Granted: September 18, 2014
Application Number:
20140281275
Various aspects provide for implementing a cache coherence protocol. A system comprises at least one processing component and a centralized controller. The at least one processing component comprises a cache controller. The cache controller is configured to manage a cache memory associated with a processor. The centralized controller is configured to communicate with the cache controller based on a power state of the processor.
METHOD AND APPARATUS FOR GAPPING
Granted: September 18, 2014
Application Number:
20140266339
Systems and methods for generating gapped signals comprising a Delta Sigma Modulator (DSM) configured to generate gapping control signals used to control gap removal rates of an associated gapping unit. The DSM is configured to generate a gapping control signal based on a value of an overflow resulted from performing adding a first number with a remainder of a stored value modulo a second number. The gap removal rates as well as the gap removal resolutions can be adjusted by selecting…
SYSTEM BOOT WITH EXTERNAL MEDIA
Granted: August 21, 2014
Application Number:
20140237223
Various aspects of the present disclosure provide for a system that is able to boot from a variety of media that can be connected to the system, including SPI NOR and SPI NAND memory, universal serial bus (“USB”) devices, and devices attached via PCIe and Ethernet interfaces. When the system is powered on, the system processor is held in a reset mode, while a microcontroller in the system identifies an external device to be booted, and then copies a portion of boot code from the…
LARGE RECEIVE OFFLOAD FUNCTIONALITY FOR A SYSTEM ON CHIP
Granted: August 21, 2014
Application Number:
20140233588
Various aspects provide large receive offload (LRO) functionality for a system on chip (SoC). A classifier engine is configured to classify one or more network packets received from a data stream as one or more network segments. A first memory is configured to store one or more packet headers associated with the one or more network segments. At least one processor is configured to receive the one or more packet headers and generate a single packet header for the one or more network…
LOW LATENCY MULTIPLEXING FOR OPTICAL TRANSPORT NETWORKS
Granted: August 14, 2014
Application Number:
20140226980
Techniques for multiplexing and demultiplexing signals for optical transport networks are presented. A network component comprises a multiplexer component that multiplexes a plurality of signals having a first signal format to produce a multiplexed signal in accordance with a second signal format, while maintaining error correction code (ECC) of such signals and without decoding such signals and associated ECC. The multiplexer component interleaves the plurality of signals with stuffing…
QUEUE REQUEST ORDERING SYSTEMS AND METHODS
Granted: July 31, 2014
Application Number:
20140215181
The described systems and methods can facilitate efficient and effective information storage. In one embodiment a system includes a hash component, a queue request order component and a request queue component. The hash component is operable to hash a request indication. The queue request order component is operable to track a queue request order. The request queue component is operable to queue and forward requests in accordance with direction from the queue request order component. In…
METHOD FOR USING A PHOTODETECTOR HAVING A BANDWIDTH TUNED HONEYCOMB CELL PHOTODIODE STRUCTURE
Granted: July 31, 2014
Application Number:
20140209801
A photodetector with a bandwidth-tuned cell structure is provided. The photodetector is fabricated from a semiconductor substrate that is heavily doped with a first dopant. A plurality of adjoining cavities is formed in the semiconductor substrate having shared cell walls. A semiconductor well is formed in each cavity, moderately doped with a second dopant opposite in polarity to the first dopant. A layer of oxide is grown overlying the semiconductor wells and an annealing process is…
DOMAIN PROTECTION AND VIRTUALIZATION FOR SATA
Granted: July 17, 2014
Application Number:
20140201481
Various aspects provide for a hardware SATA virtualization system without the need for backend and frontend drivers and native device drivers. A lightweight SATA virtualization handler can run on a specialized co-processor and manage requests enqueued by individual VMs. The lightweight SATA virtualization handler can also perform the scheduling of the requests based on performance optimizations to reduce seek time as well as based on the priority of the requests. The specialized…
PROGRAMMABLE RESISTANCE-MODULATED WRITE ASSIST FOR A MEMORY DEVICE
Granted: June 26, 2014
Application Number:
20140177356
Providing for improved write processes of a semiconductor memory are disclosed herein. By way of example, a programmable write assist can be provided that includes partially discharging a supply voltage applied to a memory cell. Partially discharging the supply voltage can improve write speeds to the memory cell, as well as improve reliability of the write process. A write assist circuit can cause the discharging in response to a resistance-modulated signal. Moreover, the…
METHOD FOR MANUFACTURING A PHOTODETECTOR HAVING A BANDWIDTH TUNED HONEYCOMB CELL PHOTODIODE STRUCTURE
Granted: May 29, 2014
Application Number:
20140147945
A photodetector with a bandwidth-tuned cell structure is provided. The photodetector is fabricated from a semiconductor substrate that is heavily doped with a first dopant. A plurality of adjoining cavities is formed in the semiconductor substrate having shared cell walls. A semiconductor well is formed in each cavity, moderately doped with a second dopant opposite in polarity to the first dopant. A layer of oxide is grown overlying the semiconductor wells and an annealing process is…
METHOD AND SYSTEM FOR MARKING SUBSTRATE AND PLACING COMPONENTS FOR HIGH ACCURACY
Granted: May 1, 2014
Application Number:
20140115886
A method and system for pre-marking a substrate to provide a visual reference enabling repetitive and accurate component placement on one or more substrates. The method for marking includes determining a first location on a substrate for placing a component relative to a cut outline of the substrate. The method includes placing a fiducial at a second location on the substrate to provide a known dimensional reference to the first location, such that the fiducial and the first location are…
MINI SAS HD CONNECTOR
Granted: May 1, 2014
Application Number:
20140120787
An apparatus including top and bottom portions that when mated form a connector. The top portion includes a top connector portion including a first wall, a second wall opposite the first wall, a first top cap connecting the first and second walls, and wherein the first wall comprises a first concave/convex feature for interlocking. The bottom portion includes a bottom connector portion configured to mate with the top connector portion to form the connector. The bottom connector portion…
