Jitter and wander reduction apparatus
Granted: May 1, 2007
Patent Number:
7212599
The present invention is for an apparatus that receives input data at a non-uniform first data rate carried by a system clock, and provides output data at a substantially uniform second data rate that is nominally equal to the first data rate and is also carried by the system clock. The system clock is faster than the first or second data rates and accordingly, a write enable signal controls the input data that is written into a saturating elastic store and a read enable signal controls…
System and method for tolerating control link faults in a packet communications switch fabric
Granted: April 24, 2007
Patent Number:
7209453
A system and method are provided for tolerating control link faults in a packet communications switch fabric. The method comprises: accepting information packets including a plurality of cells, at a plurality of port card ports, the plurality of information packets addressing a plurality of port card ports; selectively connecting port card ports to port card backplane data links; in response to backplane control link communications, selectively connecting port card backplane data links…
Modified gain non-causal channel equalization using feed-forward and feedback compensation
Granted: April 17, 2007
Patent Number:
7206342
A modified gain system and method are provided for non-causal channel equalization using feed-forward and feedback compensation. The method comprises: receiving a serial data stream first bit (present) input; comparing a second bit (past) value, received prior to the first bit input, to a third bit (future) value received subsequent to the first bit input; modifying the amplitude of the first bit input to compensate for the effect of the second and third bit values being equal; and,…
Expanding a software program by insertion of statements
Granted: April 17, 2007
Patent Number:
7207032
Every function that is called (“called function”) is expanded by insertion of several statements at the entry and exit thereof. Moreover, a calling function may also be expanded, by insertion of statements prior to and/or subsequent to a statement in which a called function is invoked. Many of the statements that are inserted contain new variables (called “synthetic variables”) to which registers are allocated during register allocation; the synthetic variables are not part of…
Serializer with programmable delay elements
Granted: March 27, 2007
Patent Number:
7197053
A two-bit serializer circuit as described herein includes programmable delay elements having adjustable phase delay that allows for phase tuning of two parallel input signals relative to an output multiplexer select signal. The two parallel input signals are retimed relative to a reference clock signal, and one of the retimed signals is processed by a fixed delay element. This delayed intermediate signal is further delayed using one programmable delay element; the other retimed signal is…
Differential receiver circuit with electronic dispersion compensation
Granted: March 13, 2007
Patent Number:
7190742
The invention describes a number of differential, balanced high-speed circuits that permit the design of a receiver with Electronic Dispersion Compensation (EDC) on a single semiconductor substrate, including the functions of an analog Fast Forward Equalizer (FFE), a Clock and Data Recovery, a Decision Feedback Equalizer (DFE), enhanced by additional circuits that permit control of the slicing level to compensate for pulse distortion, and control of the phase offset to set the optimal…
Storage system with disk drive power-on-reset detection
Granted: March 6, 2007
Patent Number:
7188225
A disk array controller reliably detects disk drive power-on-reset events that may cause a disk drive that has uncommitted write data stored in its cache to lose such data. The methods for detecting the power-on-reset events include operating the disk drives in an ATA security mode in which a power-on-reset of a disk drive will cause the drive to enter a locked state in which data transfer commands are aborted; and tracking power cycle count attributes of the disk drives over time. When…
High speed circuits for electronic dispersion compensation
Granted: February 27, 2007
Patent Number:
7184478
The invention describes a number of differential, balanced high-speed circuits that permit the design of a receiver with Electronic Dispersion Compensation (EDC) on a single semiconductor substrate, including the functions of an analog Fast Forward Equalizer (FFE), a Clock and Data Recovery, a Decision Feedback Equalizer (DFE), enhanced by additional circuits that permit control of the slicing level to compensate for pulse distortion, and control of the phase offset to set the optimal…
Use of different color sequences for variables of different sizes and different semantics
Granted: February 27, 2007
Patent Number:
7185329
Colors to be used in register allocation are grouped into a number of sequences. Each sequence is associated with an attribute (e.g. size and/or type) of variables whose nodes in an interference graph can be colored by colors in the sequence. In certain embodiments, in addition to the above-described grouping, colors within a group are ordered in a sequence. The specific order that is used may depend on, for example, an attribute (such as size) and a predetermined preference. One example…
Efficient asynchronous stuffing insertion and destuffing removal circuit
Granted: February 20, 2007
Patent Number:
7180914
A digital communications system that can asynchronously map/de-map digital signals from one clock domain to another, while reducing mapping jitter levels and permitting higher levels of integration. The digital communications system includes an asynchronous stuff bit insertion circuit, an asynchronous stuff bit removal circuit, and a communications network connected therebetween. The asynchronous stuff bit insertion circuit includes a first elastic store, a barrel shifter, and a stuffing…
Monitoring of resources that are being modeled by simulation or emulation
Granted: January 9, 2007
Patent Number:
7162401
Whenever a resource being modeled is accessed, an indication about the access is stored in a number of memory locations of a corresponding number of applications that are interested in monitoring the resource. The memory locations (also called “monitoring memory locations”) are individually identified for each application when allocating a location in main memory. At this time, a pointer to the monitoring memory location is supplied to the application and also added to a group of…
System and method for translating overhead bytes in a multidimensional digital frame structure
Granted: January 2, 2007
Patent Number:
7158535
A system and method have been provided for translating digitally wrapped communications between networks using different protocols. This invention makes use of an integrated circuit (IC) relay with programmable features to modify the locations and functions of overhead bytes between the receive and transmit sides of the device, permitting two dissimilar networks to be bridged. That is, the IC relay converts frame formatting from one frame structure to another, so that incompatible…
Method and apparatus to suspend and resume on next instruction for a microcontroller
Granted: December 26, 2006
Patent Number:
7155718
In a computer system including at least one microcontroller, by suspending tasks after execution of particular instructions, such as a load-register-from-external-memory instruction, or when a resource is not ready, unnecessary attempts to execute subsequent instruction can be avoided. If a processor register has not yet been loaded and the next instruction attempts to use that register, the task will suspend. A task can also be suspended by incorporating a computer instruction that…
Hogge phase detector with adjustable phase output
Granted: December 19, 2006
Patent Number:
7151814
A system and method are provided for adjusting the phase output of a Hogge phase detector. The method comprises: using a Hogge phase detector, generating a reference signal; using the Hogge phase detector, generating a phase and reference signals; accepting an adjust signal; modifying the amplitude of the phase signal in response to the adjust signal; integrating the amplitude modified phase signal; using the integrated signal as a phase adjusted signal; integrating the reference signal;…
Non-causal channel equalization
Granted: December 12, 2006
Patent Number:
7149938
A system and method are provided for non-causal channel equalization in a communications system. The method comprises: establishing three thresholds; receiving a binary serial data stream; comparing the first bit estimate in the data stream to a second bit value received prior to the first bit; comparing the first bit estimate to a third bit value received subsequent to the first bit; data stream inputs below the first threshold and above the third threshold are a “0” if both the…
Flexible differential interconnect cable with isolated high frequency electrical transmission line
Granted: December 5, 2006
Patent Number:
7145411
A high speed flexible interconnect cable includes a number of conductive layers and a number of dielectric layers. Conductive signal traces, located on the conductive layers, combine with the dielectric layers to form one or more high speed electrical transmission line structures. The transmission line structure may be realized as a grounded coplanar waveguide structure, a microstrip structure, a stripline structure, or the like. The cable can be coupled to destination components using a…
System and method for five-level non-causal channel equalization
Granted: November 21, 2006
Patent Number:
7139325
A system and method are provided for five-level non-casual channel equalization in a communications system. The method comprises: receiving a non-return to zero (NRZ) data stream input; establishing a five-level threshold; comparing the first bit estimate to a second bit value received prior to the first bit; comparing the first bit estimate to a third bit value received subsequent to the first bit; and, in response to the comparisons, determining the value of the first bit. Establishing…
Distributed clock network using all-digital master-slave delay lock loops
Granted: November 21, 2006
Patent Number:
7139348
A distributed clock circuit for clocking high speed data at various different physical locations on a chip while improving setup and hold times. The clock circuit includes a master delay lock loop (DLL) circuit configured to lock a global clock signal with a first data signal, and output a clock delay control signal when the global clock signal is locked. The clock circuit further includes one or more slave DLL circuits, coupled to receive the clock delay control signal to lock a local…
Digital delay lock loop for setup and hold time enhancement
Granted: October 31, 2006
Patent Number:
7130367
A digital delay lock loop (DLL) circuit for receiving parallel data and clock signals, deserializing the high speed parallel data to low speed data, and for improving setup and hold times. A DLL circuit for an N-bit datapath, includes a clock DLL configured to provide a clock signal pulse within an eye opening of each of N data signals. The DLL circuit further includes N data DLLs, each being configured to adjust a delay of a data signal to substantially center the eye opening of the…
System to provide fractional bandwidth data communications services
Granted: October 24, 2006
Patent Number:
7126956
A system to provide fractional bandwidth data transmission includes a network processor, physical layer device, or link layer device {“data device”) and a plurality of link layer devices that are coupled to a plurality of input-output ports. The link layer devices are coupled in a serial daisy chain fashion and pass data via a plurality of data channels. The first linked layer device is coupled to the data device and receives data therefrom and the last linked layer device is coupled…
