System and method for adjusting a non-return to zero data stream input threshold
Granted: September 12, 2006
Patent Number:
7107499
A state machine method and system are provided for determining non-causal channel equalization thresholds. The method comprises: receiving a non-return to zero (NRZ) data stream encoded with forward error correction (FEC); setting x=0; in State 0, adjusting a third threshold (Vopt) in response to corrected bit errors; if x=0, setting a first and second threshold equal to the third threshold; in State 1, if x=0, simultaneously adjusting the first threshold and the second threshold, to…
Digital information hiding techniques for use with data streams carried over a data communication network
Granted: September 12, 2006
Patent Number:
7106862
A data communication system transports a sequence of digital data frames that convey client input data encoded with secondary data. The system can utilize known, proprietary, or future techniques for digital data encoding, digital watermarking, data encryption, or the like. The secondary data can be frame alignment data, private data intended only for certain destination devices, and/or other data types. In a practical embodiment, the data frames are compliant with optical transport…
System and method for half-rate clock phase detection
Granted: September 5, 2006
Patent Number:
7103131
A system and method for half-rate phase detecting are provided. The method comprises: receiving binary data; dividing the data by two; latching the divided data with a first half-rate clock, creating Q1; latching the divided data with a second half-rate clock, the inverse of the first clock, creating Q2; latching Q1 with the second clock, creating Q3; latching Q2 with the first clock, creating Q4; XORing Q1 and Q2 to create phase signals; and, XORing Q3 and Q4 to create reference…
DC balanced error correction coding
Granted: September 5, 2006
Patent Number:
7103830
Two types of codings are integrated, instead of performing each coding independently. The two codings may be integrated by interleaving one or more acts of one coding method (e.g. data coding) between two or more acts of the other coding method (e.g. line coding). In some embodiments, partitioning of a block of data (e.g. a byte) for line coding (e.g. DC balance coding) is done prior to data coding (e.g. error correction coding). In such embodiments, the remaining acts of line coding may…
Reordering of out-of-order packets
Granted: July 4, 2006
Patent Number:
7072342
Tasks are assigned to process packets, but the tasks may not process the packets in the order in which the packets were received. Thus, the order of the packets may be lost during processing. The packets, however, should still be transferred in the order in which the packets were received. Therefore, reordering is performed. In particular, the reordering is performed by having tasks write commands for packets into command buffers of a command queue based on a packet sequence number of a…
System and method for the transport of backwards information between simplex devices
Granted: July 4, 2006
Patent Number:
7072361
A system and method are provided for transporting backward information in a digital wrapper format network of connected simplex devices. The system comprises a first simplex processor receiving downstream messages with overhead bytes. The first simplex processor selectively replaces overhead bytes with calculated overhead bytes and supplies the calculated overhead bytes. The system further comprises a buffer receiving the calculated overhead bytes from the first simplex processor and…
Fault-tolerant digital communications channel having synchronized unidirectional links
Granted: July 4, 2006
Patent Number:
7073001
A method of synchronizing or initiating channel lock in a serial loop formed by an initializing transceiver and subject transceivers disclosed. Should a transceiver in the serial loop detect that its receiving serial channel is desynchronized, it sends an unlock signal to the next transceiver in the loop. The unlock signal guarantees that the next transceiver's receiving serial channel will be desynchronized. Only the initializing transceiver may initiate a channel lock sequence.
Method for non-causal channel equalization
Granted: June 20, 2006
Patent Number:
7065685
A system and method are provided for non-causal channel equalization in a communications system. The method comprises: establishing a first threshold (V1) to distinguish a high probability “1” first bit estimate; establishing a second threshold (V0) to distinguish a high probability “0” first bit estimate; establishing a third threshold (Vopt) to distinguish first bit estimates between the first and second thresholds; receiving a non-return to zero (NRZ) data stream; comparing…
High speed linear half-rate phase detector
Granted: June 6, 2006
Patent Number:
7057418
A high-speed, half rate phase detector provides an effective solution to the problem of XOR gate response to the minimum width signal precursors (Q1 and Q2) of a phase signal that indicates a phase difference between a data signal and a clock signal by combining the precursor signals in a multiplexer and combining the multiplexed signal with the data signal in an XOR gate. This affords the transition information in the transitions of the precursor signals, which is significant of phase…
System and method for paralleling digital wrapper data streams
Granted: June 6, 2006
Patent Number:
7058090
A system and method are provided for paralleling data streams in a G.709 network of connected integrated circuits. The system comprises a demultiplexer for receiving a first digital wrapper data stream having a first data rate. The demultiplexer demultiplexes the first data stream into a second plurality of digital wrapper data streams having a second data rate, less than the first data rate. A second plurality of processors each accept a corresponding one of the second plurality of data…
System and method for programming the quantity of frame synchronization words in a multidimensional digital frame structure
Granted: May 30, 2006
Patent Number:
7054336
A system and method have been provided for programming synchronization features of a multidimensional digital frame structure. Such a frame structure acts as a digital wrapper and includes overhead, payload, and forward error correction (FEC) sections. Words in the overhead section are used to synchronize the frame structure. The described invention permits the quantity of the frame synchronization bytes (FSBs) to be made programmable, so that the system and method are flexible for…
Systems and methods for multi-tasking, resource sharing and execution of computer instructions
Granted: May 30, 2006
Patent Number:
7055151
In a multi-tasking pipelined processor, consecutive instructions are executed by different tasks, eliminating the need to purge an instruction execution pipeline of subsequent instructions when a previous instruction cannot be completed. The tasks do not share registers which store task-specific values, thus eliminating the need to save or load registers when a new task is scheduled for execution. If an instruction accesses an unavailable resource, the instruction becomes suspended,…
Feed-forward/feedback system and method for non-causal channel equalization
Granted: May 30, 2006
Patent Number:
7054387
A system and method are provided for feed-forward/feedback non-causal channel equalization in a communications system. The method comprises: receiving a non-return to zero (NRZ) data stream input; using three thresholds, estimating a first bit in the data stream; using two thresholds, determining a third bit value received subsequent to the first bit; comparing the first bit estimate to the third bit value; comparing the first bit estimate to a second bit value received prior to the…
System and method for temporal analysis of serial data
Granted: May 16, 2006
Patent Number:
7046742
A system and method are provided for temporally analyzing serial input data. The method comprises: establishing three thresholds; distinguishing present (first) high probability one bit value estimates; distinguishing present high probability zero bit value estimates; and, using a temporal analysis of bit values to distinguish indefinite present bit value estimates. Using a temporal analysis of bit values includes: distinguishing a present bit estimate below first threshold and above the…
Full rate error detection circuit for use with external circuitry
Granted: May 9, 2006
Patent Number:
7042961
A system and method are provided for selecting an optimal threshold detection level for a single serial data input receiver. The method comprises: receiving a serial data stream of pseudorandom binary information; using a plurality of threshold detection levels, estimating bit values; comparing the differences between estimated bit values; and, adjusting the threshold levels to minimize the difference between comparisons of estimated bit values. In some aspects, comparing the differences…
Buffer semaphore system and method
Granted: May 2, 2006
Patent Number:
7039725
A system and method are provided for securely buffering overhead messages in a network-connected integrated circuit. The method comprises: receiving messages including overhead bytes; collecting overhead bytes; creating a first overhead message from the collected overhead bytes; establishing a overhead message semaphore; and, saving the first overhead message until it is read, in response to the semaphore. Saving the first overhead message until it is read means not overwriting the first…
Transposable frame synchronization structure
Granted: April 25, 2006
Patent Number:
7035292
A method is provided for organizing a communications frame structure with selectable synchronization words. The frame structure includes a header section for overhead bits. The number of bits, position of those bits, and the content of the bits used for synchronization of the frame structure are selected from the header section for use in transmitting information. On the receiving end of the transmission, the same number, position, and content of bits are selected to synchronize the…
Optical transport network frame structure with dynamically allocable in-band data channel and forward error correction byte capacity
Granted: April 11, 2006
Patent Number:
7028241
An optical transport network data frame structure is configured to provide an in-band data channel. The in-band channel data is contained in the data frame space that would otherwise be allocated to forward error correction (“FEC”) bytes. Consequently, the provision of the in-band data channel does not affect the number of client data bytes contained in the data frame structure. In accordance with a practical embodiment, the data frame structure is compliant with IaDI specifications…
System and method for selectively scrambling multidimensional digital frame structure communications
Granted: April 4, 2006
Patent Number:
7023881
A system and method have been provided to increase security in scrambled communications by periodically changing the seed masks used to generate the scrambling algorithms at the transmitter and receiver. The scrambling algorithm is changed by periodically modifying the seed masks which establishes the initial state of the scrambling algorithm generators. The same seed mask key is passed through an auxiliary communication channel to the receiver to insure that matching descrambling…
System and method for non-causal channel equalization
Granted: April 4, 2006
Patent Number:
7024599
A system and method are provided for non-causal channel equalization in a communications system. The method comprises: receiving a non-return to zero (NRZ) data stream input; establishing thresholds to distinguish a first bit estimate; comparing the first bit estimate in the NRZ data stream to a second bit value received prior to the first bit, and a third bit received subsequent to the first bit; in response to the comparisons, determining the value of the first bit; tracking the NRZ…
