System and method for hierarchical switching
Granted: March 28, 2006
Patent Number:
7020131
A system and method have been provided for hierarchically arbitrating in a broadband information switching network. The method promotes the fair and efficient distribution of information packets across the switch fabric that ultimately permits the switch to maximally match information packets to switch output addresses, at faster rates and higher throughput. The method comprises: accepting variably sized information packets at a plurality of switch inputs, that address a plurality of…
Time slot interchanging of time slots from multiple SONET signals without first passing the signals through pointer processors to synchronize them to a common clock
Granted: March 21, 2006
Patent Number:
7016344
A SONET multiplexed system architecture that permits greater levels of integration. The architecture includes a time slot interchanger for routing information from at least one SONET input signal path associated with a respective first time slot to at least one SONET output signal path associated with a respective second time slot. Each input signal path includes a pointer interpreter, and each output signal path includes a FIFO buffer serially coupled to a pointer generator. The…
System and method for switch timing synchronization
Granted: February 21, 2006
Patent Number:
7002996
A system and method have been provided for synchronizing the timing of line cards and switch cards in a broadband switch. Synchronization is accomplished using an auxiliary data link between the line and switch cards. One of the switch cards is selected as the master switch card. The master switch card receives timing information from the line cards, and in turn, sends timing correction signals to each of the line cards. Each line card acquires synchronization using its respective timing…
Method and apparatus for improving data integrity and desynchronizer recovery time after a loss of signal
Granted: February 14, 2006
Patent Number:
6999480
An apparatus and corresponding method for preventing data loss in network devices is disclosed. The present invention monitors an incoming data stream to a network device, or devices, and in the event that an error condition is detected, predetermined error data is inserted into the data stream, wherein the predetermined error data is provided at the same data rate as the recovered data rate internal to the network device. Thus, the network device will not have to adjust to a different…
System and method for generating forward error correction based alarms
Granted: January 31, 2006
Patent Number:
6993700
A system and method are provided for generating alarms from forward error correction (FEC) data in a G.709 network-connected integrated circuit. The method includes: receiving messages including forward error correction bytes; using the forward error correction bytes to detect errors in the messages; and, generating alarm signals in response to the detected errors. Generating alarm signals in response to the detected errors includes generating a signal degrade (SD) signal in response to…
System and method for generating a reference clock
Granted: January 10, 2006
Patent Number:
6985552
A system and method are provided for synchronizing a reference clock to a pseudorandom non-return to zero (NRZ) data stream in a clock data recovery system. The method comprises: sampling a pseudorandom NRZ data stream; determining a mean frequency of transitions (Fd) in the data stream; determining a transition probability (P) associated with the mean frequency of transitions; using a phase/frequency detector responsive to a VCO frequency, the mean frequency of transitions, and the…
Shared resource access via declarations that contain a sequence number of a packet
Granted: December 20, 2005
Patent Number:
6978330
Logic (also called “re-ordering semaphore”) issues semaphore grants to access a shared resource in an order different from the order in which semaphore requests for accessing the shared resource are received. The re-ordering semaphore needs to receive a semaphore release between any two semaphore grants. There is no limit on the duration between a semaphore grant and a semaphore release, so that a task that receives a semaphore grant can use the shared resource for any length of…
System and method for programming the value of frame synchronization words in a multidimensional digital frame structure
Granted: December 6, 2005
Patent Number:
6973099
A system and method have been provided for programming synchronization features of a multidimensional digital frame structure. Such a frame structure acts as a digital wrapper, and includes overhead, payload, and forward error correction (FEC) sections. Words in the overhead section are used to synchronize the frame structure. The described invention permits the value of the frame synchronization bytes (FSBs) to be made programmable, so that the system and method are flexible for changes…
System and method for programming the location of frame synchronization words in a multidimensional digital frame structure
Granted: December 6, 2005
Patent Number:
6973100
A system and method have been provided for programming synchronization features of a multidimensional digital frame structure. Such a frame structure acts as a digital wrapper, and includes overhead, payload, and forward error correction (FEC) sections. Words in the overhead section are used to synchronize the frame structure. The described invention permits the location of the frame synchronization bytes (FSBs) to be made programmable, so that the system and method are flexible for…
Phase adjustment system and method for non-causal channel equalization
Granted: November 22, 2005
Patent Number:
6968480
A system and method is provided for using phase adjustment in non-causal channel equalization in a communications system. The method comprising: receiving a serial data stream input; comparing a bit value in the serial data stream determined at a first phase with respect to a clock, to a bit value determined at a second phase; determining the optimal phase for the determination of bit values; and, using the optimal phase to determine subsequently received bit values. Typically, the…
System and method for programming the bit error rate of frame synchronization words in a multidimensional digital frame structure
Granted: November 15, 2005
Patent Number:
6965618
A system and method have been provided for programming synchronization features of a multidimensional digital frame structure. Such a frame structure acts as a digital wrapper, and includes overhead, payload, and forward error correction (FEC) sections. Words in the overhead section are used to synchronize the frame structure. The described invention permits the bit error rate (BER) of the frame synchronization bytes (FSBs) to be made programmable, so that the system and method are…
System and method for segmenting a multidimensional digital frame structure
Granted: November 1, 2005
Patent Number:
6961350
A system and method have been provided to segment communications between relay nodes in a network using digitally wrapped, or frame structure communications. The overhead bytes in the frame are given special functions, to enable processes such as synchronization or an auxiliary communications channel. Overhead byte quantities, locations, values, or combinations of the above are used to signal the processes. Nodes in the network can be selectively programmed to recognize the overhead byte…
System and method for redundant path connections in digital communications network
Granted: November 1, 2005
Patent Number:
6961366
A system and method for providing redundancy in an integrated circuit (IC) relay device has been disclosed. The relay device accepts communications on a first and second receive path. The relay device monitors communications on both the receive paths, and selects a path having a high degree of integrity. Likewise, the relay selectively supplies communications on a first and second transmit path. The relay device selects the transmit path having the proper measure of communication…
Systems and methods for non-casual channel equalization in an asymmetrical noise environment
Granted: November 1, 2005
Patent Number:
6961390
A system and method are provided for non-causal channel equalization in a communications system. The method comprises: receiving a non-return to zero (NRZ) data stream input; establishing thresholds to distinguish a first bit estimate; comparing the first bit estimate in the NRZ data stream to a second bit value received prior to the first bit, and a third bit received subsequent to the first bit; in response to the comparisons, determining the value of the first bit; tracking the NRZ…
Self-synchronous data scrambler
Granted: October 4, 2005
Patent Number:
6952480
An encryption system has been provided to self-synchronously scramble communications where the receiver must recover the clock information from the data stream, such as the SONET format. To prevent jamming during initialization, or during times when no data is being transferred, flags and overhead data are scrambled, along with the payload. Timing controls to the scrambler permit this scrambler to be selectively engagable, so that the selective overhead scrambling becomes a second layer…
Stackable test apparatus for protecting integrated circuit packages during testing
Granted: September 27, 2005
Patent Number:
6949817
A stackable test apparatus is disclosed including a body having a first surface with a raised portion extending from the first surface along a perimeter of the body and a plurality of stacking pins extending away from the first surface arraigned in a stacking pin pattern. Also included is a plurality of stacking pin receivers located on a second surface of the body, the stacking pin receivers arraigned in a pattern to match the stacking pin pattern and sized to accept the stacking pin.
Memory co-processor for a multi-tasking system
Granted: August 30, 2005
Patent Number:
6938132
A co-processor (also called “memory co-processor”) provides an interface to a memory, by executing instructions on data held in the memory. The co-processor uses a specified address to fetch data from memory, performs a specified instruction (such as incrementing a counter or policing) on the data to obtain modified data, and writes the modified data back to memory at the same address. Depending on the embodiment, the memory co-processor may include a first buffer for holding…
System and method for selectively broadcasting a multidimensional digital frame structure
Granted: August 16, 2005
Patent Number:
6931006
A system and method have been provided for programming synchronization features of a multidimensional digital frame structure. Such a frame structure acts as a digital wrapper and includes overhead, payload, and forward error correction (FEC) sections. Words in the overhead section are used to selectively synchronize the broadcast frame structure at a plurality of network nodes. The described invention permits the frame synchronization bytes (FSBs) to be made programmable, so that the…
System and method for non-causal channel equalization using error statistic driven thresholds
Granted: July 5, 2005
Patent Number:
6915464
A system and a method are provided for non-causal channel equalization using error statistics. The method comprises: receiving a non-return to zero (NRZ) data stream input encoded with forward error correction (FEC); establishing a plurality of thresholds to generate a first bit estimate; comparing the first bit estimate in the data stream to a second bit value received prior to the first bit; comparing the first bit estimate to a third bit value received subsequent to the first bit; in…
Circuit with voltage clamping for bias transistor to allow power supply over-voltage
Granted: June 28, 2005
Patent Number:
6911871
A ring oscillator stage includes two differential transistor pairs configured to add an adjustable amount of delay to a differential input signal. Each differential pair is biased with a bias current transistor; the bias current transistor is “protected” by a voltage-clamping transistor that limits the drain voltage of the bias current transistor. The voltage-clamping transistors enable use of a power supply voltage (VDD) that would otherwise exceed the reliability breakdown voltage…
