System and method for partitioning resources in a system-on-chip (SoC)
Granted: November 18, 2014
Patent Number:
8893267
In a system-on-chip (SoC), a method is provided for partitioning access to resources. A plurality of processors is provided, including a configuration master (CM) processor, a memory, a plurality of OSs, and accessible resources. The method creates a mapping table with a plurality of entries, each entry cross-referencing a range of destination addresses with a domain ID, where each domain ID is associated with a corresponding processor. Access requests to the resource are accepted from…
Operating system with hardware-enabled task manager for offloading CPU task scheduling
Granted: November 4, 2014
Patent Number:
8881161
An operating system (OS) is provided including a hardware-based task scheduler, with a method for managing OS sourced tasks to be performed by a central processing unit (CPU). An OS, partially enabled as software instructions stored in a computer-readable medium and executed by the CPU, generates CPU tasks. The CPU tasks are buffered in a computer-readable task database memory. CPU task IDs associated with the buffered CPU tasks are enqueued in a CPU queue. Subsequently, the CPU dequeues…
System-on-chip with feedback loop for processor frequency control
Granted: October 21, 2014
Patent Number:
8868956
A system and method are provided for using feedback to control processor frequencies in a system-on-chip (SoC). The method is associated with an SoC having a processor operating frequency responsive to a processor supply voltage on a first SOC interface, and a controller for managing the operating frequency. The controller accepts a frequency selection command associated with a first operating frequency, at a second SoC interface. The controller sends a first voltage command associated…
Transmitters and receivers using a jitter-attenuated clock derived from a gapped clock reference
Granted: October 7, 2014
Patent Number:
8855258
A system and method are provided for resynchronizing a transmission signal using a jitter-attenuated clock derived from an asynchronous gapped clock. A first-in first-out (FIFO) memory accepts an asynchronous gapped clock derived from a first clock having a first frequency. The gapped clock has an average second frequency less than the first frequency. The input serial stream of data is loaded at a rate responsive to the gapped clock. A dynamic numerator (DN) and dynamic denominator (DD)…
Outstanding load miss buffer with shared entries
Granted: September 30, 2014
Patent Number:
8850121
A load/store unit with an outstanding load miss buffer and a load miss result buffer is configured to read data from a memory system having a level one cache. Missed load instructions are stored in the outstanding load miss buffer. The load/store unit retrieves data for multiple dependent missed load instructions using a single cache access and stores the data in the load miss result buffer. The outstanding load miss buffer stores a first missed load instruction in a first primary entry.…
Single carrier-frequency-division multiple access (SC-FDMA) physical uplink control channel (PUCCH) 2/2a/2b detection
Granted: September 30, 2014
Patent Number:
8848686
A system and method are provided for Single Carrier-Frequency-Division Multiple Access (SC-FDMA) Physical Uplink Control Channel (PUCCH) format 2/2a/2b detection. A receiver accepts a plurality of multicarrier signals transmitted simultaneously from a plurality of transmitters, with overlapping carrier frequencies. For each multicarrier signal, a single tap measurement of time delay is performed using a Direction of Arrival (DoA) technique. After performing a back-end processing…
Cut-through packet stream encryption/decryption
Granted: September 16, 2014
Patent Number:
8838999
A system and method are provided for the cut-through encryption of packets transmitted via a plurality of input/output (IO) ports. A system-on-chip is provided with a first plurality of input first-in first out (FIFO) memories, an encryption processor, and a first plurality of output FIFOs, each associated with a corresponding input FIFO. Also provided is a first plurality of IO ports, each associated with a corresponding output FIFO. At a tail of each input FIFO, packets from the SoC…
System and method for process, voltage, temperature (PVT) stable differential amplifier transfer function
Granted: September 9, 2014
Patent Number:
8829995
A method is provided for process, voltage, temperature (PVT) stable transfer function calibration in a differential amplifier. The gain resistors of a differential amplifier are initially selected to achieve a flat amplitude transfer function in the first frequency band. After calibration, the degeneration capacitor is connected and tuned until a peaked amplitude transfer function is measured, which is resistant to variations in PVT. As an alternative, the degeneration capacitor is not…
Frequency synthesis with gapper
Granted: August 26, 2014
Patent Number:
8816730
Systems and methods for frequency synthesis using a gapper. A frequency synthesizer may comprise a gapper, a first integer divider and a Phase Locked Loop (PLL). When a frequency of an output signal is intended to be greater than a corresponding input signal, a factor can be borrowed by the gapper from the first integer divider to generate a rational divide ratio G that is greater 1 in order for the gapper to be capable of performing the division by G. The PLL is capable of multiplying a…
Dynamic memory module switching with read prefetch caching
Granted: August 12, 2014
Patent Number:
8806140
A system and method are provided for using a system-on-chip (SoC) memory manager to optimize the use of off-chip memory modules. A SoC memory controller receives a request for a first data block, subsequent to shutting the first memory down, and determines that the first data block is stored in the first memory. A SoC memory switching core uses a memory map to translate the first data block address in the first memory module to a first data block address in the second memory module. If…
Load store unit with load miss result buffer
Granted: August 12, 2014
Patent Number:
8806135
A load/store unit with an outstanding load miss buffer and a load miss result buffer is configured to read data from a memory system having a level one cache. Missed load instructions are stored in the outstanding load miss buffer. The load/store unit retrieves data for multiple dependent missed load instructions using a single cache access and stores the data in the load miss result buffer. When missed load instructions are reissued from the outstanding load miss buffer, data for the…
Load miss result buffer with shared data lines
Granted: July 29, 2014
Patent Number:
8793435
A load/store unit with an outstanding load miss buffer and a load miss result buffer is configured to read data from a memory system having a level one cache. Missed load instructions are stored in the outstanding load miss buffer. The load/store unit retrieves data for multiple dependent missed load instructions using a single memory access and stores the data in the load miss result buffer. The load miss result buffer includes dependent data lines, dependent data selection circuits,…
Network-attached storage (NAS) bandwidth manager
Granted: July 29, 2014
Patent Number:
8793334
A system and process are provided for managing bandwidth in a network-attached storage (NAS) system. The process provides a NAS storage device having a network interface, at least one storage drive, a controller head, and a NAS bandwidth manager application enabled as software instructions. The process receives a request for access to a file system share from a client via a network having a maximum throughput rate. The NAS bandwidth manager identifies the client and provides client…
Optimized chromatic dispersion filter
Granted: July 29, 2014
Patent Number:
8792789
A method is provided for performing chromatic dispersion (CD) compensation. A zero-forcing filter is calculated with a number of taps (n) required to nullify a chromatic dispersion frequency response of an optical channel. The number of taps in the zero-forcing filter is truncated to a number equal to (n?x), where x is an integer greater than 0. In one aspect, the chromatic dispersion frequency response of the optical channel is partitioned into a plurality of constituent chromatic…
System-on-chip with thermal management core
Granted: July 22, 2014
Patent Number:
8786449
A system and method are provided for using a thermal management core to control temperature on a system-on-chip (SoC). The method provides an SoC with an internal thermal management core and an internal temperature sensor. For example, the sensor may be located on or near a processor core die. The thermal management core monitors temperatures recorded by the SoC temperature sensor, and sends commands for controlling SoC device functions. In response to these commands, the thermal…
Latch isolation circuit
Granted: July 22, 2014
Patent Number:
8786319
A system and method have been provided for passively isolating a latch circuit. The method provides a latch having a first input, an output, and a reset port. The latch first input is selectively connected to a first reference voltage. While the latch first input is connected to the first reference voltage, the latch is reset. Subsequent to disconnecting the latch first input from the first reference voltage, a first node is selectively connecting to the latch first input. In response to…
System and method for selecting a power supply source
Granted: July 8, 2014
Patent Number:
8772966
A power supply source selection circuit is provided with a comparator and a switch. The comparator has an input to accept a first reference voltage directly proportional to a bandgap reference voltage. For example, the bandgap voltage may be derived from a battery voltage. The comparator has an input to accept a second reference voltage directly proportional to a first supply voltage (e.g., a line voltage), and an output to supply a switch signal in response to comparing the second…
Pattern-based optical lens testing apparatus having a module comparing a viewed image representation to a copy of target pattern and method for using the same
Granted: July 1, 2014
Patent Number:
8766165
A pattern method is provided for testing an optical lens. The method provides a lens for test, including a first lens surface with a focal plane in object space and a second lens surface with a focal plane in image space. Also provided is a pattern test fixture including an imaging device and a target pattern. The lens is positioned so that the imaging device is located outside the object space focal plane and the target pattern located is outside the image space focal plane. The imaging…
Packet forwarding system and method using patricia trie configured hardware
Granted: July 1, 2014
Patent Number:
8767757
A method is provided for forwarding packets. Using a control plane state machine, addresses in a packet header are examined to derive a pointer value. The pointer value is used to access entries in a result database to identify routing information, a buffer pool ID associated with a location in memory, and a queue ID. A direct memory access (DMA) engine writes the packet into the memory location in response to the first message including the buffer pool ID. The QM prepares a second…
Device and method for a multiplexor/demultiplexor reset scheme
Granted: July 1, 2014
Patent Number:
8766681
Circuit and method for resetting clock circuitry. The circuit includes a chain of cascading units, each of which receives an input of a number of parallel bit streams and outputs a different number of parallel bit streams. A chain of dividers provides one or more divided clock signals to the cascading units, wherein the divided clock signals are based on a gated common clock signal. An asynchronous reset signal is delivered to the dividers, and when asserted sets the dividers to a reset…
