System and method for integrated circuit die size reduction
Granted: June 24, 2014
Patent Number:
8762915
A circuit analysis tool is provided for die size reduction analysis. A processor determines a first initial output slack time. If the first initial output slack time is greater than zero, a first circuit element is modeled with a second die area, less than the first die area. The second die area is associated with a third delay greater than the first delay. Then, the second data signal is modeled equal to the first data signal with the third delay. If a first modified output slack time…
Frequency synthesis with low resolution rational division
Granted: June 24, 2014
Patent Number:
8762436
A method is provided for synthesizing signal frequencies using low resolution rational division. A reference frequency value and synthesized frequency value are accepted. In response to dividing the synthesized frequency value by the reference frequency value, an integer value numerator (n) and an integer value denominator (d) are determined, with n/d=I(N/D)=I+N/D=(I+1)?(D?N)/D), and where N/D<1. An accumulator creates a sum of (D?N) and a count from a previous cycle, and creates a…
System and method for updating a data structure
Granted: June 24, 2014
Patent Number:
8762362
System and method for updating a data structure are disclosed. In one embodiment, the method includes providing a data structure that includes a hierarchically arranged set of nodes and branches, and each node has two or less branches, retrieving a first data entry in the data structure via a first node in response to a first data access request, modifying the data structure to generate a first intermediate data structure that keeps the first node and creates a duplicate of the first…
System and method for the aggregation of 10GBASE-R signals into pseudo 100GBASE-R signals
Granted: June 24, 2014
Patent Number:
8761209
An Ethernet physical layer (PHY) module is provided with a method for transceiving between a 10GBASE-R client interface and a 100G attachment interface. On each of ten client interface logical lanes a 10GBASE-R signal is accepted. Each 10GBASE-R logical lane is demultiplexed into two 5 gigabit per second (Gbps) pseudo 100GBASE-R logical lanes, creating a total of twenty pseudo 100GBASE-R logical lanes. The pseudo 100GBASE-R logical lanes are arranged into n groups of 20/n pseudo…
Two wavelength range photodiode demultiplexer and methods for using the same
Granted: June 10, 2014
Patent Number:
8748797
A method is provided for demultiplexing optical signals. A first photodiode accepts first optical signals in a first range of wavelengths with second optical signals in a second range of wavelengths greater than the first range. First electrical signals are generated in the first photodiode in response to the first optical signals. A second photodiode accepts the second optical signals, and generates second electrical signals in response to the second optical signals. The first…
Linear source follower amplifier
Granted: June 3, 2014
Patent Number:
8742849
A linear source follower amplifier is provided with a first metal-oxide semiconductor (MOS) field effect transistor (FET) having a gate to accept an ac input signal and a source to supply an ac output signal. A second MOS FET has a gate to accept the ac input signal, a source connected to the drain of the first MOS FET. A third MOS FET has a drain connected to the source of the first MOS FET, a gate connected to the drain of the second MOS FET, and a source connected to a first reference…
Ultra low-noise true sub-volt band gap
Granted: June 3, 2014
Patent Number:
8742746
A method and device are disclosed for providing an ultra low-noise hand gap voltage reference. The method detects a first voltage drop across a first diode reference, and a second voltage drop across a second voltage reference that includes a second diode. The first and second voltage drops are compared. Temperature compensation currents are supplied to the first diode reference and second voltage references in addition to constant currents, where the constant currents have the same…
Full duplex wire-line transceiver with echo cancellation line driver
Granted: May 27, 2014
Patent Number:
8737278
A full-duplex wire-line transceiver is provided with echo cancellation line driver. The transceiver has an impedance matching network with a network interface, and a transmit interface to accept a differential transmit signal for transmission via the network. The impedance matching network has a receive interface to supply a differential receive signal accepted at the network interface, where the transmit interface is coupled to the receive interface. A hybrid circuit has an input to…
System and method for packet splitting
Granted: May 20, 2014
Patent Number:
8732351
A data structure splitting method is provided for processing data using a minimum number of memory accesses. An SoC is provided with a with a central processing unit (CPU), a system memory, an on-chip memory (OCM), and a network interface including an embedded direct memory access (DMA). The network interface accepts a data structure with a header and a payload. The DMA writes the payload in the system memory, and the header in the OCM. The network interface DMA notifies the CPU of the…
System and method for adaptively configuring an L2 cache memory mesh
Granted: April 22, 2014
Patent Number:
8706966
A system and method are provided for adaptively configuring L2 cache memory usage in a system of microprocessors. A system-on-chip (SoC) is provided with a plurality of n selectively enabled processor cores and a plurality of n L2 cache memories. The method associates each L2 cache with a corresponding processor core, and shares the n L2 caches between enabled processor cores. More explicitly, associating each L2 cache with the corresponding processor core means connecting each processor…
Photodetector with a bandwidth-tuned cell structure
Granted: March 25, 2014
Patent Number:
8680639
A photodetector with a bandwidth-tuned cell structure is provided. The photodetector is fabricated from a semiconductor substrate that is heavily doped with a first dopant. A plurality of adjoining cavities is formed in the semiconductor substrate having shared cell walls. A semiconductor well is formed in each cavity, moderately doped with a second dopant opposite in polarity to the first dopant. A layer of oxide is grown overlying the semiconductor wells and an annealing process is…
Fractional phase-locked loop with dynamic divide ratio adjustment
Granted: March 18, 2014
Patent Number:
8674731
Systems and methods for Phase-Locked Loop (PLL) based frequency synthesizer comprising a dynamic fraction divider in a feedback loop. The dynamic fraction divider employs a dynamic divide ratio that dynamically changes with the jitters and noise spurs contained in an input signal to the PLL, and generates a feedback signal used to adjust the PLL output frequency. The dynamic divide ratio may be determined by comparing the phases of the PLL output signal and the input signal.
Network synchronized time base timer
Granted: March 11, 2014
Patent Number:
8670467
A system and method are provided for synchronizing a programmable timer time base and external time signal. The method either accepts or supplies an external time signal (e.g., IEEE 1588) at an external interface, links a synchronized time base to the external time signal, and clocks a channel time base with the synchronized time base. Then, a timer channel can be used to perform programmable timer functions in response to the channel time base. Some programmable timer functions include…
System and method for residence time calculation
Granted: March 11, 2014
Patent Number:
8670466
A system and method are provided for residence time calculations in a network communications local device. A network interface module in the local device receives a first packet from a network-connected remote device. A timing module in the local device records an arrival time of the first packet with respect to a local reference clock. The timing module tracks adjustments in the local reference clock and records a known departure time, with respect to the local reference clock, of when…
Jitter-attenuated clock using a gapped clock reference
Granted: March 4, 2014
Patent Number:
8666011
A system and method are provided for generating a jitter-attenuated clock using an asynchronous gapped clock source. The method accepts a first reference clock having a first frequency. Using the first reference clock, an asynchronous gapped clock is generated having an average second frequency less than the first frequency. A dynamic numerator (DN) and dynamic denominator (DD) are iteratively calculated for the gapped clock. Then, DN and DD are averaged. In response to the averaging, an…
Uplink single carrier frequency division multiple access multiple-input multiple-output soft interference cancellation receiver
Granted: March 4, 2014
Patent Number:
8665693
A system and method are provided for Soft Interference Cancellation (SIC) in receiving Single Carrier Frequency Division Multiple Access (SC-FDMA) Multiple-Input Multiple Output (MIMO) signals. A receiver with Mr antennas accepts multicarrier signals transmitted simultaneously, with N overlapping carrier frequencies. The receiver removes a cyclic prefix (CP), and fast Fourier transforms (FFT) the multicarrier signal from each antenna, supplying Mr number of N-tone signals y. Using either…
Symmetric diagonal interleaving and encoding/decoding circuit and method
Granted: February 11, 2014
Patent Number:
8650464
A circuit and method form a codeword including parity and message bits, as follows. Each codeword has a first part in a current sequence (e.g. a current OTN-row) that is to be now transmitted and second part spread across multiple past sequences (e.g. previously prepared and transmitted OTN-rows). The codewords are grouped into multiple groups such that each codeword within a group has no bit in common with another codeword in that group. Moreover, each codeword has a bit in common with…
System and method for closed-loop optical network power backoff
Granted: February 11, 2014
Patent Number:
8649686
In a communication device using a plurality of signal enhancement mechanisms, a system and method are provided for managing signal processing power consumption. A receiver accepts a communications signal and analyzes signal integrity. In response to analyzing the signal integrity, a signal enhancement mechanism is changed, and device power consumption is modified in response to changing the signal enhancement mechanism. In one aspect, the receiver changes a receiver signal enhancement…
Asynchronous extension to serializer/deserializer frame interface (SFI) 4.2
Granted: February 11, 2014
Patent Number:
8649394
A system and method are provided for transmitting and receiving asynchronous channels of information via a SerDes Frame Interface (SFI) 4.2 interface. The SerDes device accepts a plurality of channels operating at asynchronous channel clock rates. Bytes of data from each channel are loaded into a source at the channel clock rates. Once loaded, the bytes of data for each channel are drained from the source at a line clock rate and interleaved into four 64-bit segments. A 2-bit control…
Accelerated data uploading
Granted: February 4, 2014
Patent Number:
8645503
A method and system are provided for accelerated data uploading to a remote service device destination. An on-line (third party) storage device receives an upload request message from a network-connected client device. A unique first descriptor in a descriptor field of the upload request message is accessed and compared to a list of descriptors maintained by the on-line storage device. If the accessed first descriptor is on the list, a first file is read that is stored in the on-line…
