Transparent in-band forward error correction for signal conditioning-encoded signals
Granted: August 7, 2012
Patent Number:
8239738
A system and method are provided for framing messages in a forward error correction (FEC) structure for data streams encoded with redundant signal conditioning information. The method accepts signal conditioning-encoded words at a first bit rate, and eliminates redundant information in the signal conditioning-encoded words, creating N reduced-bit words of k bits. The k-bit words are mapped into a payload field of N*(k/p) p-bit words. Overhead (OH) and FEC parity fields are generated, and…
Multiuser multiple-input multiple-output (MU-MIMO) channel estimation for multicarrier communications
Granted: August 7, 2012
Patent Number:
8238496
Provided are a system and method of estimating channels for a plurality of multicarrier signals in a wireless receiver. A receiver accepts a plurality of multicarrier signals, transmitted simultaneously from a plurality of transmitters, with overlapping carrier frequencies and nominally orthogonal reference signals. For each multicarrier signal, a reference signal is recovered including a plurality of adjacent subcarrier frequencies carrying predetermined symbols. A channel estimate is…
System and method for pre and post-tap zeroing
Granted: July 24, 2012
Patent Number:
8228975
A system and method are provided for zeroing pre and post-tap settings in a link partner using a plurality of voltage gain taps. The method provides a link partner (LP) transmitter. A network-connected local device (LD) selects an LP pre-tap or post-tap. The LD also chooses a zero gain setting for the selected LP tap. In a first iteration, the LD directs the LP to decrease the difference between the selected tap gain setting and the zero setting by 1 step. If a limit signal is not…
10 GbE LAN signal mapping to OTU2 signal
Granted: July 17, 2012
Patent Number:
8223638
A high-capacity digital communications system and method of transporting 10 GbE LAN packets between user devices over an OTN network that allows the packets to be transported in a manner that is transparent to the destination device(s) on the network. The digital communications system includes an OTN network, and at least one source device and at least one destination device connected to the network via respective 10Gbase-R interfaces. The system transports 10 GbE LAN data packets over…
Data slicer threshold adjustment for disparity controlled signals
Granted: July 10, 2012
Patent Number:
8218685
A system and method are provided for using disparity measurements to control the adjustment of a data slicer threshold. The method receives a serial stream of pseudorandom digital data signals having an average DC value, and compares data signal amplitudes to a slicer threshold value. In response to the slicer threshold value comparison, data signal “1” and “0” values are determined. A first sum of determined “1” values is created, and a second sum of determined “0”…
Virtual lane forward error correction in multilane distribution
Granted: June 19, 2012
Patent Number:
8205141
A system and method are provided for generating virtual lane (VL) forward error correction (FEC) overhead (OH) in a communication multi-lane distribution (MLD) protocol transmitter, and for recovering data words from virtual lanes with FEC OH in an MLD protocol receiver. The transmission method accepts an Optical Transport Network (OTN) frame with n consecutively ordered payload chunks of data words, at a first data rate. Each payload chunk is assigned to a virtual lane data word (VLDW)…
Victim net crosstalk reduction
Granted: June 19, 2012
Patent Number:
8205181
A circuit analysis tool is provided, enabled with software instructions, for minimizing circuit crosstalk. The instructions provide a first circuit connected to an output mode, having a last gate with a plurality of inputs and an output. The instructions calculate a first circuit victim net delay range (timing window) having a minimum delay (Vmin) and a maximum delay (Vmax). A second circuit is provided having an output connected to the output node to supply an aggressor net delay range…
System and method for free space optical connector alignment
Granted: June 12, 2012
Patent Number:
8200094
A method and system are provided for aligning the optic port of a device having a Free Space Optics (FSO) connector. In a link device with an FSO connector, a controller determines that an optic port alignment procedure is required. A lens is set to an initial wide beam dispersion mode, and a mirror is set to an initial position angle. Note: the lens and mirror may be the FSO connector receive path or transmit path. An optical signal is communicated at a first low baud rate, and the…
Transporting asynchronous ODUk signals over a synchronous interface
Granted: June 5, 2012
Patent Number:
8195049
System and methods are provided, in an Optical Transport Network (OTN), for communicating asynchronous Tributary Slots (TSs) via a synchronous Optical Payload Transport Unit of level k (OTUk) interface. The transmission method accepts a plurality of TSs at a corresponding plurality of asynchronous data rates. The TSs are mapped, using a tangible memory medium, into pseudo-Optical channel Data Tributary Unit (ODTU) frames synchronized to a common clock. Then, the synchronized pseudo-ODTU…
Using domains for physical address management in a multiprocessor system
Granted: May 29, 2012
Patent Number:
8190839
A multi-processor computer system is provided for managing physical memory domains. The system includes at least one processor having an address interface for sending a memory access message, which includes an address in physical memory and a domain identification (ID). The system also includes a physical memory portioned into a plurality of domains, where each domain includes a plurality of physical addresses. A domain mapping unit (DMU) has an interface to accept the memory access…
Curve tracer signal conversion for integrated circuit testing
Granted: May 29, 2012
Patent Number:
8188760
A curve tracer signal conversion device is provided. The signal conversion device has an input connected to the curve tracer base port to accept a repeating sequence of stepped base signals. The conversion device has a signal input connected to either the curve tracer collector or emitter port, typically the collector. The conversion device has a plurality of signal outputs, where each signal output is sequentially connected to the selected (i.e. collector) curve tracer port in response…
System and method for identifying a non-predetermined input data rate
Granted: May 22, 2012
Patent Number:
8184685
A system and method are provided for identifying the data rate of an input signal in a communications receiver. The method supplies a candidate frequency from a list of potential input data rate frequencies. A first test is performed, attempting to phase-lock a coded input data signal using a reference signal at the candidate frequency. If the input signal is phase-locked, a second test is performed of monitoring a phase detector output signal for the occurrence of a phase-lock…
Timer with network synchronized time base
Granted: May 15, 2012
Patent Number:
8179924
A system and method are provided for synchronizing a programmable timer time base and an external time signal. The method either accepts or supplies an external time signal (e.g., IEEE 1588) at an external interface, links a synchronized time base to the external time signal, and clocks a channel time base with the synchronized time base. Then, a timer channel can be used to perform programmable timer functions in response to the channel time base. Some programmable timer functions…
Clock and data recovery loop with ISI pattern-weighted early-late phase detection
Granted: May 15, 2012
Patent Number:
8180011
An inter-symbol interference (ISI) pattern-weighted early-late phase detector is provided. I and Q clocks are generated, where the Q clock has a fixed phase delay with respect to the I clock. The I clock frequency is divided by n, creating a reference clock. A serial data stream is sequentially sampled with the I and Q clocks, creating digital I-bit and Q-bit values, respectively. The I-bit values and Q-bit values are segmented into n-bit digital words. In response to analyzing the I-bit…
ISI pattern-weighted early-late phase detector with function-controlled oscillation jitter tracking
Granted: May 15, 2012
Patent Number:
8180012
An inter-symbol interference (ISI) pattern-weighted early-late phase detector is provided. An I clock and a function-controlled oscillation cycle phase delay Q clock are generated. The I clock frequency is divided by n, creating a reference clock. A serial data stream is sequentially sampled with the I clock, and with the function-controlled varied phase delay Q clock, creating digital I-bit and varied phase delay Q-bit values, respectively. The values are segmented into n-bit digital…
ISI pattern-weighted early-late phase detector with jitter correction
Granted: May 8, 2012
Patent Number:
8175207
An inter-symbol interference (ISI) pattern-weighted early-late phase detector is provided. I and Q clocks are generated. The I clock frequency is divided by n, creating a reference clock. A serial data stream is sequentially sampled with the I clock, and with Q clocks having fixed and varied phase delays from the I clock, creating digital I-bit and Q-bit values. The I-bit values and Q-bit values are segmented into n-bit digital words. I clock phase corrections are identified and a…
Multi-domain management of a cache in a processor system
Granted: May 8, 2012
Patent Number:
8176282
A system and method are provided for managing cache memory in a computer system. A cache controller portions a cache memory into a plurality of partitions, where each partition includes a plurality of physical cache addresses. Then, the method accepts a memory access message from the processor. The memory access message includes an address in physical memory and a domain identification (ID). A determination is made if the address in physical memory is cacheable. If cacheable, the domain…
Multi-channel optical transport network training signal
Granted: April 17, 2012
Patent Number:
8160057
Systems and methods are provided for multi-channel ITU G.709 optical transport network (OTN) communications. The transmission method accepts an ITU G.709 OTN frame including an OTU overhead (OH) section and an ODU section. A forward error correction (FEC) parity section with a training signal is appended to the ITU G.709 OTN frame, to create a training-enhanced (TE) OTN frame. All, or a portion of the TE OTN may be buffered in a tangible memory medium in preparation for striping. The…
System-on-chip communication manager
Granted: April 10, 2012
Patent Number:
8155134
A Queue Manager (QM) system and method are provided for communicating control messages between processors. The method accepts control messages from a source processor addressed to a destination processor. The control messages are loaded in a first-in first-out (FIFO) queue associated with the destination processor. Then, the method serially supplies loaded control messages to the destination processor from the queue. The messages may be accepted from a plurality of source processors…
Duty-cycle feedback charge pump
Granted: April 3, 2012
Patent Number:
8149031
A charge pump includes a reference charge pump with an input interface to accept a phase detector signal and a duty-cycle feedback signal, and an output to supply a control voltage. A replica charge pump accepts the phase detector signal supplies the duty-cycle feedback signal. If the reference charge pump source current (Ip) becomes mismatched with the sinking current (In), non-equal Tn and Tp time periods may result. The phase detector accepts reference and data signals having a steady…
