Distributed file system with client-side deduplication capacity
Granted: March 19, 2013
Patent Number:
8402250
A system and method are provided for deduplication (dedup) of data file information in a network of distributed data filers. A host, including a metadata service (MDS) and a data node (DN), receives a block count and hash group calculations for a file from a network-connected client device. The MDS creates a file map with target addresses, and compares the calculated hash group to hash groups associated with stored blocks of data in a global dedup hash table. If a match is found, the MDS…
Integrated circuit module time delay budgeting
Granted: March 12, 2013
Patent Number:
8397197
A circuit analysis tool is provided, enabled as computer software instructions, for budgeting time delays between integrated circuit (IC) modules. The instructions accept a command enabling an IC floor-plan including a first module and a second module. The first module includes a first circuit element having a signal output interface, and an output port. The second module includes an input port, and a second circuit element having a signal input interface. A command is accepted defining…
System and method for laser patterning an integrated circuit etching mask
Granted: March 12, 2013
Patent Number:
8394244
A method is provided for laser patterning an integrated circuit (IC) etching mask. The method provides an IC packaged die with a first region underlying a backside surface of a bulk silicon (Si) layer. An etch-resistant film is formed overlying the backside surface. Alternately, the entire IC die package is conformally coated. A semi-transparent film is formed overlying the etch-resistant film, semi-transparent to light having a first wavelength. In response to irradiating the…
Equalizer with automatic gain control (AGC)
Granted: March 5, 2013
Patent Number:
8391349
A combination equalizer and automatic gain control (AGC) is provided for high-speed receivers. The combination circuit comprises a first AGC having an input to accept a communication signal and an input to accept a first control signal. The first AGC modifies the communication signal gain in response to the first control signal, to supply a first stage signal at an output. An equalizer has an input to accept the first stage signal and an input to accept a second control signal. The…
Digital CMOS circuit with noise cancellation
Granted: February 26, 2013
Patent Number:
8384421
A system is provided with a digital complementary-metal-oxide-semiconductor (CMOS) device and a noise cancellation circuit. The CMOS device has a first interface to accept a binary logic input signal, a second interface to accept a source current, a third interface to supply a binary logic output signal, and a fourth interface connected to a first dc voltage (e.g., ground) to sink current. A first resistor is interposed between a second dc voltage (e.g., Vdd), with a potential higher…
Parallel forward error correction with syndrome recalculation
Granted: February 26, 2013
Patent Number:
8386894
A system and method are provided for parallel processing data that is forward error correction (FEC) protected with multiple codewords. The method accepts an electrical waveform representing a digital wrapper frame of interleaved FEC codewords. Typically, the codeword encoding is solved using an algorithm such as linear block codes, cyclical block codes, Hamming, Reed-Solomon, or Bose-Chaudhuri-Hocquenghem (BCH). The method calculates a first set of syndromes for a first codeword. In…
Integrated circuit transmission line
Granted: February 19, 2013
Patent Number:
8377749
A method is provided for fabricating a transmission line between electrical circuits. The method initially provides a first electrical circuit with a signal interface and a reference voltage interface, and a second electrical circuit with a signal interface and a reference voltage interface. The first circuit signal interface is connected to the second circuit signal interface with a metal wire. An insulator coating (e.g., poly-para-xylylene) is formed, encapsulating the wire. Then, an…
Ethernet PHY level security
Granted: February 12, 2013
Patent Number:
8375201
A system and method are provided for securing links at the physical (PHY) layer in an IEEE 802.3 Ethernet communication system. A local device (LD) receives an electrical waveform representing link partner security information from a network-connected link partner (LP) via unformatted message pages. The LD accesses predetermined LP reference information stored in a tangible memory medium. The LD compares the received LP security information to the LP reference information. In response to…
Adaptive phase-locked loop (PLL) multi-band calibration
Granted: January 22, 2013
Patent Number:
8358159
Adaptive multi-band frequency calibration is provided for a phase-locked loop (PLL). A voltage controller oscillator (VCO) is initially selected nominally associated with first synthesized signal frequency, where the VCO is selected from a plurality of n VCOs, and each VCO is tunable across a band of synthesized signal frequencies. A lock detector compares a nominal first synthesized signal frequency to a reference signal frequency. In response to sensing a difference between the nominal…
Flexible accumulator for rational division
Granted: January 1, 2013
Patent Number:
8346840
A system and method are provided for rational division. The method accepts accepting a binary numerator and a binary denominator. A binary first sum is created of the numerator and a binary first count from a previous cycle. A binary first difference is created between the first sum and the denominator. In response to comparing the first sum with the denominator, and first carry bit is generated and added to a first binary sequence. The first binary sequence is used to generate a k-bit…
System and method for encoding using common partial parity products
Granted: January 1, 2013
Patent Number:
8347169
A system and method are provided for creating codewords using common partial parity products. The method initially accepts an algorithm for creating p indexed parity bit positions, where the parity bit for each position is calculated from mathematical operations performed on bits from n indexed user word positions. A first group of parity bit positions is found, where the parity bit for each position in the first group is calculated using at least a first number of common mathematical…
Narrowband interference cancellation method and circuit
Granted: December 11, 2012
Patent Number:
8331508
A narrowband interference (NBI) canceller is coupled to an A/D converter to receive an input signal and supply an NBI-canceled signal to an error correcting decoder. In the NBI canceller, a first arithmetic unit receives the input signal and a predicted-interference signal, and supplies a difference thereof as the interference-canceled signal. A slicer receives the interference-canceled signal and supplies a decision signal. A second arithmetic unit subtracts the decision signal from the…
System and method for transmitter training
Granted: October 2, 2012
Patent Number:
8279915
A system and method are provided for ordering tap setting modifications in a link partner using a plurality of voltage gain taps, while avoiding minimum and maximum limitations. Provided is a link partner (LP) transmitter having a parallel selectable voltage gain taps. The method sends messages from a network-connected local device (LD) directing the LP to generally change the gain setting of either the pre-tap or the post-tap, as follows. The gain setting of selected tap is changed in…
Laser optical path detection
Granted: September 18, 2012
Patent Number:
8268669
A method is provided for detecting laser optical paths in integrated circuit (IC) packages. The method provides an IC die encapsulated as a package in a compound of glass spheres and epoxy. Power is supplied to the IC. The IC is scanned with a laser. Typically, a laser wavelength is used that is minimally absorbed by the glass spheres in the epoxy compound of the IC package, and changes in current to the IC are detected. A detected current change is cross-referenced against a scanned IC…
Frequency integrator with digital phase error message for phase-locked loop applications
Granted: September 11, 2012
Patent Number:
8264388
A digital phase-locked loop (DPLL), a supporting digital frequency integrator, and a method are provided for deriving a digital phase error signal in a DPLL. A digital frequency integrator periodically accepts a digital tdcOUT message from a Time-to-Digital Converter (TDC) representing a measured ratio of a reference clock (Tref) period to a synthesizer clock (Tdco) period. Also accepted is a digital message selecting a first ratio (Nf). In response, a digital phase error (pherr) message…
System and method for accelerated forward error correction (FEC) synchronization
Granted: August 28, 2012
Patent Number:
8255779
A system and method are provided for accelerating forward error correction (FEC) synchronization in a communicating receiver. On the transmitter side, the method accepts an energy waveform representing a packet of data symbols, encodes the packet, and creates an FEC block. Prior to transmitting the FEC block, an electromagnetic waveform is transmitted representing an FEC flag character. Then, an electromagnetic waveform representing the FEC block is transmitted a predetermined first…
Lock detection using a digital phase error message
Granted: August 21, 2012
Patent Number:
8248106
A system and method are provided for frequency lock detection using a digital phase error. A lock detection module accepts a digital phase error (pherr) message proportional to an error in phase between a reference clock and a (synthesizer clock*Nf). Also accepted is a unitless frequency error tolerance value (?f). The lock detection module periodically supplies a lock detect signal, indicating whether the synthesizer clock frequency is within the frequency error tolerance value of the…
System and method for Ethernet per priority pause packet flow control buffering
Granted: August 21, 2012
Patent Number:
8248945
A method is provided for managing a transmit buffer using per priority pause flow control. An Ethernet transceiver generates packet descriptors identifying packets to be transmitted that are stored in memory. A priority is assigned to each descriptor and associated packet. Each descriptor is loaded into a queue having a queue priority associated with the descriptor priority. In response to accessing a first descriptor, output from a selected first priority queue, a first packet…
Ethernet to multilane optical transport network traffic interface
Granted: August 21, 2012
Patent Number:
8249080
A system and method are provided for transporting a serial stream via a lower speed network using multiple parallel paths. At a transmitter, an optical or electromagnetic waveform is accepted representing a serial stream of digital information, and unbundled into n virtual information streams. Each virtual information stream is divided into a sequence of segments. Each segment is encapsulated, creating a sequence of packets by adding a start indicator to the beginning of each segment,…
Multichannel polarization control for polarization multiplexed optical transport networks
Granted: August 14, 2012
Patent Number:
8244143
A system and method are provided for calibrating orthogonal polarity in a multichannel optical transport network (OTN) receiver. The method accepts a composite signal and separates the polarization of the signal into a pair of 2n-phase shift keying (2n-PSK) modulated input signals via Ix and Qx optical signal paths, where n?1. Likewise, a pair of 2p-PSK modulated input signals are accepted via Iy and Qy optical signal paths where p?1. Polarization-adjusted I?x, Q?x, I?y, and Q?y signals…
