NON-VOLATILE MEMORY CHARGE PUMP FOR RADIO FREQUENCY IDENTIFICATION (RFID) SYSTEM
Granted: December 2, 2010
Application Number:
20100301122
A charge pump is incorporated into circuitry of an RFID tag. The charge pump takes advantage of an antenna voltage phase to eliminate the need for a charge pump clock generator. Placement of the charge pump in the RFID circuitry reduces the number of pump stages and eliminates drivers used in each pump stage. In some implementations, an RFID tag comprises antenna circuitry, including a tuned antenna, for receiving an RF signal. Voltage conversion circuitry in the RFID tag is coupled to…
CYCLIC DIGITAL TO ANALOG CONVERTER
Granted: November 11, 2010
Application Number:
20100283651
Some embodiments include apparatus and methods having an amplifier, a capacitor network coupled to the amplifier, and switching circuitry coupled to the amplifier and the capacitor network. The switching circuit is configured to successively apply a selected reference voltage selected from among a first reference voltage, a second reference voltage, and a third reference voltage to the capacitor network in response to a digital input code to generate an output voltage. Additional…
THRESHOLD VOLTAGE METHOD AND APPARATUS FOR ESD PROTECTION
Granted: November 4, 2010
Application Number:
20100277841
An electrostatic discharge protection circuit comprises a comparator coupled between a power supply terminal and ground. The comparator responds to an electrostatic discharge event producing a trigger signal at a comparator output. The comparator comprises a first and second current mirror. The first and second current mirrors each comprise a sense device and a mirror device. The mirror devices are coupled in series between the power supply terminal and ground. The first mirror device…
Current-Controlled Hysteretic Oscillator
Granted: October 28, 2010
Application Number:
20100271143
The disclosed current-controlled hysteretic oscillator operates by controlled currents opposing each other in differential pairs to set a controlled hysteresis for improved relaxation oscillations with immunity to phase or frequency error.
SURFACE MOUNTING CHIP CARRIER MODULE
Granted: October 21, 2010
Application Number:
20100263922
A device includes a carrier and an integrated circuit chip having a first side supported by the carrier and a second side having contacts. The carrier has multiple carrier contacts supported by the carrier and separated from the integrated circuit chip. Multiple leads are coupled between the contacts on the integrated circuit chip and the multiple carrier contacts. A resin encapsulates the integrated circuit chip leaving the multiple carrier contacts at least partially uncovered for…
Two-Dimensional Position Sensor
Granted: October 14, 2010
Application Number:
20100258360
A two dimensional position sensor having a touch-sensitive panel defined by a single-layer electrode pattern arranged on one side of a substrate. The electrode pattern is made up of ‘n’ electrode units extending row-wise over the panel. Each electrode unit is made up of a single drive electrode extending across the touch-sensitive area of the panel and a plurality of ‘m’ sense electrodes, which collectively laterally extend across the touch-sensitive area and individually each…
QUADRATURE DECODER FILTERING CIRCUITRY FOR MOTOR CONTROL
Granted: October 14, 2010
Application Number:
20100262880
The disclosed quadrature decoder filtering circuitry for motor control uses one quadrature signal to correct an error in the other quadrature signal, thus allowing a noisy signal due to large dust particles or scratches to be recovered. In some implementations, a system processing for quadrature signals comprises a first circuitry triggered by edges of a first quadrature signal to detect inactivity of a second quadrature signal during consecutive edges of the first quadrature signal. A…
VOLTAGE GENERATOR FOR MEMORY ARRAY
Granted: September 30, 2010
Application Number:
20100246282
A high voltage may be generated for programming memory cells in a memory array. A middle voltage may also be generated for reading memory cells in the memory array. Control logic and switches may be used to select between the high voltage and the middle voltage. A first oscillator generates clock signals at a high frequency for generating the voltages, and a low frequency oscillator may be used to generate pulses at a lower frequency than the first oscillator to allow the first…
METHODS AND PROCESSOR-RELATED MEDIA TO PERFORM RAPID RETURNS FROM SUBROUTINES IN MICROPROCESSORS AND MICROCONTROLLERS
Granted: September 30, 2010
Application Number:
20100250904
Various embodiments include methods and related media for performing operations including a return operation. One such method includes testing a content of a return value register and setting status flags. Testing the content of the return value register and setting the status flags are performed in response to a single instruction.
Method and Apparatus to Scramble Data Stored in Memories Accessed by Microprocessors
Granted: September 23, 2010
Application Number:
20100241874
A scrambler/descrambler module included in an integrated circuit device is operable for receiving a scrambling key and constant data that is unique to the integrated circuit device. The scrambler/descrambler module includes a first layer or circuit arrangement that uses a scrambling key to generate first scrambled data. The scrambler/descrambler module includes a second layer or second circuit arrangement that uses data that is unique to the integrated circuit device, and that is…
LOW CURRENT COMPARATOR WITH PROGRAMMABLE HYSTERESIS
Granted: September 23, 2010
Application Number:
20100237908
A low current comparator with programmable hysteresis is disclosed that uses a ratio of latch intrinsic (internal) latch capacitance and capacitance of a sample capacitor to adjust hysteresis. In some implementations, the comparator includes a switch capacitor sampling stage coupled to a dynamic latch output stage. Depending on an output state (0 or 1) of the comparator, hysteresis is generated by adding or subtracting a first charge stored in the latch intrinsic capacitance to or from a…
SMART CARD READER
Granted: September 9, 2010
Application Number:
20100224684
A card reader receives an indication that a device has been plugged into a socket of the card reader. Power is provided to the socket in accordance with a first type of device. An attempt to communicate with the device is made in accordance with a first type of device protocol. If the communication attempt is not successful, power is provided to the socket in accordance with a second type of device, and communications commence with the device in accordance with a second type of device…
ROUTABLE ARRAY METAL INTEGRATED CIRCUIT PACKAGE
Granted: September 9, 2010
Application Number:
20100224981
An integrated circuit assembly comprises an integrated circuit die, and a routable metal layer comprising metal traces linking a plurality of wire bond pads to a plurality of external connection pads such that the metal traces are routable under the die area. An electrically nonconductive adhesive layer couples the integrated circuit die to the routable metal layer, and a plurality of wire bonds link circuitry on the integrated circuit die to the wire bond pads in the routable metal…
Power Reduction in Microcontrollers
Granted: September 9, 2010
Application Number:
20100229011
The disclosed implementations provide for power reduction in microcontrollers by reactivating a clock in the microcontroller for one or more peripheral modules in response to an internal or external trigger event, thus allowing the one or more peripheral modules to respond to events while operating in a low-power sleep mode. In some implementations, one or more peripheral modules in a microcontroller provide a clock request signal to a clock generator in the microcontroller. In response…
Method and Apparatus for Sensing
Granted: September 2, 2010
Application Number:
20100219845
An apparatus for sensing a change in capacitance of a sensing electrode to a system ground, such as that which may be used to form a touch sensor, with the sensing electrode forming touch sensitive surface is arranged to include a sleep mode of operation. The apparatus includes a sample capacitor having a first terminal coupled to the sensing electrode, and a second terminal coupled to a voltage measurement circuit. The voltage measurement circuit is arranged in operation to determine a…
Capacitive Sensing
Granted: September 2, 2010
Application Number:
20100219846
A multi-channel capacitive sensor for measuring the capacitances of a plurality of sense electrodes to a system reference potential. The sensor comprises a sample capacitor having a first terminal and a second terminal, a first diode having a first terminal coupled to the second terminal of the sample capacitor and a second terminal coupled to a first sense electrode, and a second diode having a first terminal coupled to the second terminal of the sample capacitor and a second terminal…
Dual Mode, Single Ended to Fully Differential Converter Structure
Granted: September 2, 2010
Application Number:
20100219864
A dual mode, single ended to fully differential converter structure is incorporated into a fully differential sample and hold structure which can be coupled with an ADC as a front end for mixed mode applications. The structure incorporates additional switches which allow negative and positive charges to be sampled on both negative and positive sides of the structure. By inverting the sampled charge on one side, single ended to fully differential conversion is obtained. The structure can…
Key Recovery Mechanism for Cryptographic Systems
Granted: September 2, 2010
Application Number:
20100220863
A cryptographic system can include a register containing a key and a processor coupled to the register. The processor can be operable for performing a first encrypting operation, where the encrypting operation includes computing a key schedule using the register as a workspace. At the end of the first encrypting operation, the key is recovered from the register for use in a second encrypting operation.
Dummy Write Operations
Granted: September 2, 2010
Application Number:
20100223434
A dummy write operation is disclosed that mimics an actual write operation to a memory array. In some implementations, a dummy write operation mimics an actual write operation by starting a charge pump, selecting a correct data line in the memory array, and by following the sequencing of an actual write operation. By mimicking an actual write operation, an attacker cannot use power analysis to distinguish between dummy and actual write operations. For example, PIN comparison operations…
SINGLE PIN COMMUNICATION MECHANISM
Granted: September 2, 2010
Application Number:
20100223476
A method and device include a power pin, a ground pin, and a communications pin. A communications module receives power from the power pin and utilizes an edge counting communication protocol over the communication pin.
