FIFO-type one-way interfacing device between a master unit and a slave unit, and corresponding master unit and slave unit
Granted: February 8, 2007
Application Number:
20070033306
An interfacing device (23) of the type enabling one-way interfacing between a master unit (21) and a slave unit (22), includes: a memory plane managed according to a “first in, first out” mode, with write and read pointers, and making it possible to store words coming from the master unit, via an input bus (FIFODin); a bank of output registers capable of containing words read in the memory plane and providing an output signal (FIFODout) capable of being read by the slave unit; a…
VOLTAGE-CONTROLLED OSCILLATOR WITH MULTI-PHASE REALIGNMENT OF ASYMMETRIC STAGES
Granted: January 18, 2007
Application Number:
20070013455
A multi-phase realigned voltage-controlled oscillator (MRVCO) achieves phase realignment based on charge injection in the VCO stages. The individual VCO stages provide an oscillating output signals having an asymmetric waveform with substantially different rise and fall times. This ensures that the VCO as a whole has a multiphase impulse response to the charge injection that is strictly positive or strictly negative, and substantially constant so as to be independent of the VCO phase or…
Asynchronous arbitration device and microcontroller comprising such an arbitration device
Granted: January 18, 2007
Application Number:
20070016731
An arbitration device is provided, which is designed to be connected between, on the one hand, a first and a second module and, on the other hand, storing means forming a memory workspace. This arbitration device includes a detector for detecting one or more requests coming, concurrently or not, from the first and second modules, for the purpose of accessing the memory workspace.
SELECTABLE BLOCK PROTECTION FOR NON-VOLATILE MEMORY
Granted: January 18, 2007
Application Number:
20070016741
A semiconductor non-volatile memory device, particularly a flash memory array, having a chip configuration with a plurality of pins including a write protect pin, a serial in pin and an optional parallel data bus with input-output pins (I/O7-0), plus other pins, all electrically communicating with the memory array and particularly a sector protection register of variable size and location. The sector protection register defines which sectors or group of sub-sectors to protect and is…
NON-VOLATILE MEMORY ARRAY WITH SIMULTANEOUS WRITE AND ERASE FEATURE
Granted: December 21, 2006
Application Number:
20060285384
A non-volatile transistor memory array has individual cells with a current injector and a non-volatile memory transistor. Injector current gives rise to charged particles that can be stored in the memory transistor by tunneling. When a row of the array is activated by a word line, the active row has current injectors ready to operate if program line voltages are appropriate to cause charge storage in a memory cell, while a cell in an adjacent row be erased by charge being driven from a…
Method for manufacturing a metal-semiconductor contact in semiconductor components
Granted: December 14, 2006
Application Number:
20060281291
A method for manufacturing a metal-semiconductor contact in semiconductor Components is disclosed. There is a relatively high risk of contamination in the course of metal depositions in prior-art methods. In the disclosed method, the actual metal-semiconductor or Schottky contact is produced only after the application of a protective layer system, as a result of which it is possible to use any metals, particularly platinum, without the risk of contamination.
Device for comparing two words of n bits each
Granted: November 30, 2006
Application Number:
20060267739
The disclosure relates to a device for comparing two words, N and P, of n bits each. The device includes at least one comparator block comprising n basic comparator blocks which can each be used to compare bits Ni and Pi of digit place i of words N and P, whereby 0=i=n?1. Moreover, each basic comparator block comprises: a first sub-block which can be used to generate a first signal indicating whether or not bits Ni and Pi are equal, said signal being generated at the output of the…
FABRICATION OF AN EEPROM CELL WITH SiGe SOURCE/DRAIN REGIONS
Granted: November 2, 2006
Application Number:
20060244073
An EEPROM memory cell uses silicon-germanium/silicon and emitter polysilicon film for fabricating shallow source/drain regions to increase a breakdown voltage with respect to a well. The source/drain regions are fabricated to be approximately 100 nm (0.1 micrometers (?m)) in depth with a breakdown voltage of approximately 14 volts or more. A typical breakdown voltage of a well in a bipolar process is approximately 10 volts. Due to the increased breakdown voltage achieved, EEPROM memory…
Ergonomic image recorder
Granted: October 26, 2006
Application Number:
20060237625
The invention relates to small dimension image recorders, such as an image recorder, comprising a matrix of rows and columns of photosensitive points, arranged on a chip of a generally square or rectangular form with believed corners, characterised in comprising a reading register arranged at the base of the matrix. The register is bent to follow the bevelled corners of the chip and thus comprises a horizontal piece and two oblique pieces. The sensor further comprises means (ZIn) to…
Image sensor having linear abutting bars
Granted: October 26, 2006
Application Number:
20060238631
The invention relates to large-dimension linear image sensors operating by relative translation between the image and the sensor and consisting of a plurality of linear arrays abutting in a staggered fashion. In order to improve the design of the sensor, according to the invention the arrays are mounted on packages whose upper surface has an elongate rectangular shape provided on two opposite sides of the rectangle with two extensions substantially covered by the ends of the array, two…
Image sensor with rapid read cycle
Granted: October 12, 2006
Application Number:
20060227234
The invention proposes an image sensor comprising a picture capture matrix having N rows and K columns of image dots, a read register at the free end of the K columns. In order to improve the read speed of the matrix, the invention proposes that the horizontal transfer into the read register be continued even while the vertical signals for shifting from one row to the other are operative, without however continuing the horizontal transfer while the transfer gate between columns and…
ESD protection circuit with scalable current capacity and voltage capacity
Granted: October 5, 2006
Application Number:
20060220138
An ESD protection circuit includes semiconductor structures as basic elements whose electrical conductivity changes in a breakdown or avalanche manner in the presence of an applied voltage which exceeds a threshold value. The ESD protection circuit has a matrix of basic elements in which a desired current capacity can be set by specifying a number of basic elements in each row, and a desired voltage capacity can be set by specifying a number of rows.
Method for the acquisition of an image of a finger print
Granted: September 14, 2006
Application Number:
20060204061
The invention relates to the recognition of digital finger prints, more particularly to recognition by an elongate bar of sensors able to detect crests and valleys of finger prints when a finger is passed in a relative manner in front of a sensor in an essentially parallel manner in relation to the direction of elongation of said bar. The inventive method comprises the following operations: successive partially overlapping images are acquired under the control of a processor;…
Method and casting mold for producing an optical semiconductor module
Granted: September 7, 2006
Application Number:
20060196412
A method and a casting mold for producing an optical semiconductor module is provided, wherein a semiconductor body having at least one optically active element on its top is introduced into a leadframe. Then conductive connections are established between the semiconductor body and the leadframe, and then the leadframe and semiconductor body are encapsulated in a casting mold. Wherein provided in the part of the casting mold that faces the top of the semiconductor body are masking…
Switching device for at least two voltages, corresponding electronic circuit and memory
Granted: September 7, 2006
Application Number:
20060197601
A device for switching voltages includes at least two branches each allowing the voltage from a power source to be switched to a single output. Each of the said branches includes at least two transistors, of which at least one is a protective transistor with a dual function: protecting the said power source; and management of at least one leakage current, generated between at least two pins of the said protective transistor.
Selection method for data communication between base station and transponders
Granted: September 7, 2006
Application Number:
20060198327
A selection method for selecting at least one transponder located in the response area of a base station, which are linked to one another by a wireless bidirectional data communication path, in which method the base station transmits an electromagnetic carrier signal, which has at least one arbitration symbol, wherein each arbitration symbol has a query segment in which data are encoded by the base station, and has a response segment that can be used by the transponder for coding and…
Method for the integration of two bipolar transistors in a semiconductor body, semiconductor arrangement in a semiconductor body, and cascode circuit
Granted: September 7, 2006
Application Number:
20060199348
A method for the integration of two bipolar transistors in a semiconductor body, wherein, for the first bipolar transistor, a first emitter semiconductor region, a first base semiconductor region, and a first collector semiconductor region are produced. A recombination layer is applied to the first bipolar transistor, which is adjacent to the first emitter semiconductor region or the first collector semiconductor region and is constructed in such a way that charge carriers recombine on…
High frequency arrangement
Granted: August 24, 2006
Application Number:
20060186532
A high frequency arrangement is provided that includes an integrated high frequency circuit, a first bond pad, which is electrically connected by a first electrical supply line, in particular a bond wire and/or a solder bump, to a housing terminal and/or another circuit, wherein the first bond pad adjoins a dielectric so that the first bond pad forms a first capacitance with the dielectric and an electrically conductive region of the integrated high-frequency circuit, and the first…
Method for integrating an electronic component or similar into a substrate
Granted: August 24, 2006
Application Number:
20060189094
A method for integrating an electronic component or the like into a substrate includes following process steps: formation of a dielectric insulating layer on the front side of a substrate; complete back-etching of an area of the substrate from the back of the substrate to form a cavity; formation of a photoresistive layer with a homogeneous thickness over the back of the substrate; placement of an electronic component on the photoresistive layer formed in the cavity for adhesion of the…
High-voltage regulator system compatible with low-voltage technologies and corresponding electronic circuit
Granted: August 3, 2006
Application Number:
20060170407
A voltage regulator system is provided, which receives a first voltage and produces a regulated voltage. Such a device does not include any transistor supporting the first voltage, but does include transistors supporting at most a second voltage lower than the first voltage and includes division means, which include a first transistor connected in series with at least one second transistor, which division means receive the first voltage and generate the regulated voltage.
