Integrated circuit with automatic start-up function
Granted: June 28, 2007
Application Number:
20070146048
The invention relates to integrated electronic circuits, and notably to those comprising analog functions. The invention relates more particularly to a starter circuit designed to ensure the automatic start-up of a biasing circuit following an interruption in the operation of the latter. The starter circuit comprises, in an integrated circuit substrate of a first type of conductivity comprising at least one well of an opposite type of conductivity and a semiconductor region of the same…
AN ELECTRONICS PACKAGE WITH AN INTEGRATED CIRCUIT DEVICE HAVING POST WAFER FABRICATION INTEGRATED PASSIVE COMPONENTS
Granted: June 21, 2007
Application Number:
20070138572
An apparatus and a method for producing passive components on an integrated circuit device. The integrtated circuit device has post wafer fabrication integrated passive components situated on the opposite substrate side of the device's integrated circuitry. Electrical contact pads of the passive components are configured to be coupled to the electronics package contact pads to complete the electronic package.
NON-THERMAL ANNEALING OF DOPED SEMICONDUCTOR MATERIAL
Granted: June 21, 2007
Application Number:
20070141817
A method of non-thermal annealing of a silicon wafer comprising irradiating a doped silicon wafer with electromagnetic radiation in a wavelength or frequency range coinciding with lattice phonon frequencies of the doped semiconductor material. The wafer is annealed in an apparatus including a cavity and a radiation source of a wavelength ranging from 10-25 ?m and more particularly 15-18 ?m, or a frequency ranging from 12-30 THz and more particularly 16.5-20 THz.
LOW-VOLTAGE SINGLE-LAYER POLYSILICON EEPROM MEMORY CELL
Granted: June 14, 2007
Application Number:
20070133301
The present invention is an electronic memory cell and a method for the cell's fabrication comprising a first transistor configured to be coupled to a bit line. The first transistor has an essentially zero voltage drop when activated and is configured to control an operation of the memory cell. A second transistor is configured to operate as a memory transistor and is coupled to the first transistor. The second transistor is further configured to be programmable with a voltage about…
MULTI-LEVEL MEMORY CELL ARRAY WITH LATERAL FLOATING SPACERS
Granted: June 14, 2007
Application Number:
20070134875
An array of multi-level non-volatile memory transistors features a transistor construction with a conductive polysilicon control gate having opposed sidewalls insulatively spaced just above the substrate. Conductive polysilicon spacers are separated from the opposed sidewalls by thin tunnel oxide. Source and drain implants are beneath or slightly outboard of the spacers. Insulative material is placed over the structure with a hole cut above the control gate for contact by a gate…
METHOD OF MAKING A MULTI-BIT NANOCRYSTAL MEMORY
Granted: May 17, 2007
Application Number:
20070111442
A manufacturing method for an improved memory cell having a pair of non-volatile memory transistors with each transistor using a nanocrystal gate structure, the transistor pair constructed between a pair of bit line polysilicon depositions. Between the pair of non-volatile memory transistors, a word line device is interposed, allowing serial linkage of the pair of non-volatile memory transistors.
METHOD AND APPARATUS FOR A DUAL POWER SUPPLY TO EMBEDDED NON-VOLATILE MEMORY
Granted: April 19, 2007
Application Number:
20070086248
A charge pump is configured to receive an external voltage level and generate a high voltage level, wherein the high voltage level is higher than the external voltage level. A memory control circuit is configured to receive the external voltage level and the high voltage level, and to select one of the voltage levels. A memory array, with a word line and a bit line, is configured to receive the external and high voltage levels at the word line and the high voltage levels at the bit line.…
LOW-VOLTAGE SINGLE-LAYER POLYSILICON EEPROM MEMORY CELL
Granted: April 19, 2007
Application Number:
20070087550
The present invention is an electronic memory cell and a method for the cell's fabrication comprising a The first transistor configured to be coupled to a bit line. The first transistor has an essentially zero voltage drop when activated and is configured to control an operation of the memory cell. A second transistor is configured to operate as a memory transistor and is coupled to the first transistor. The second transistor is further configured to be programmable with a voltage about…
SEMICONDUCTOR DEVICE WITH A TOROIDAL-LIKE JUNCTION
Granted: April 19, 2007
Application Number:
20070087557
Formation of elements of a vertical bipolar transistor is described, in particular a vertical npn transistor formed on a p-type substrate. Accordingly, an improved method not limited by constraints of photolithography, and an ensuing device made by such methods, is described. A temporary spacer (e.g., an oxide spacer) is deposited over a dielectric separation layer. The temporary spacer and dielectric separation layers are then anisotropically etched, forming a dielectric “boot…
METHOD FOR SIMULTANEOUS FABRICATION OF A NANOCRYSTAL AND NON-NANOCRYSTAL DEVICE
Granted: April 12, 2007
Application Number:
20070080425
A method of simultaneously fabricating at least two semiconductor devices, at least bone of which is a nanocrystal memory and at least one of which is a non-nanocrystal semiconductor device. A nanocrystal layer is formed over an oxide layer of the at least two semiconductor devices being fabricated. The nanocrystal layer is removed from at least one portion of the substrate corresponding to the at least one non-nanocrystal device being fabricated. A polycrystalline gate is formed for…
SEMICONDUCTOR DEVICE WITH A TOROIDAL-LIKE JUNCTION
Granted: April 5, 2007
Application Number:
20070075400
Formation of elements of a vertical bipolar transistor is described, in particular a vertical npn transistor formed on a p-type substrate. Accordingly, an improved method not limited by constraints of photolithography, and an ensuing device made by such methods, is described. A temporary spacer (e.g., an oxide spacer) is deposited over a dielectric separation layer. The temporary spacer and dielectric separation layers are then anisotropically etched, forming a dielectric “boot…
REDUCED VOLTAGE PRE-CHARGE MULTIPLEXER
Granted: March 29, 2007
Application Number:
20070069785
An electronic device selects one of a plurality of input signals for coupling to an output channel. Individual pulldowns provide a separate pathway for each input, and are coupled to a common node which: is pre-charged to a voltage less than a system voltage. Each pulldown is coupled to a select line for gating an associated input signal.
Device for converting a complex-valued bandpass signal into a digital baseband signal
Granted: March 29, 2007
Application Number:
20070071133
A device is disclosed for converting a complex-valued bandpass signal into a digital baseband signal. In accordance with the invention, the device has: a) an analog filter unit that is designed to filter the complex-valued bandpass signal such that signal components outside of the useful band are suppressed, to produce only the real component from the filtered signal, and to provide a real-valued bandpass signal, b) one analog-to-digital converter that is connected to the analog filter…
Logic cell with two isolated redundant outputs, and corresponding integrated circuit
Granted: March 22, 2007
Application Number:
20070063728
The disclosure relates to a logic cell for an integrated circuit, including two redundant outputs, a first output equipped with an output transistor of type P and a second output equipped with an output transistor of type N. Such a cell includes isolation element connecting the first and second outputs and forming an isolation resistance.
Liquid crystal microdisplay
Granted: March 15, 2007
Application Number:
20070057890
The invention relates to liquid crystal matrix micro displays, and in particular those which are embodied on a monolithic silicon substrate in which are integrated the electronic circuits for control of a matrix array of liquid crystal cells. The matrix comprises, for each dot at the crossover of a row and of a column, an elementary electronic circuit for controlling an elementary liquid crystal cell situated at this crossover. This circuit comprises at least one storage capacitor for…
Matrix image recorder using cmos technology
Granted: March 8, 2007
Application Number:
20070052829
The invention relates to matrix image sensors intended in particular for digital photography. The invention provides a driver in each pixel that allows exposure control common to the entire matrix. The driver comprises five transistors, a photodiode and, apart from a supply conductor and a ground, four control conductors, these being an exposure control conductor common to all the pixels of the matrix; a row selection conductor common to all the pixels of any one row; a reset conductor…
SYSTEM AND METHOD FOR PROVIDING A NANOSCALE, HIGHLY SELECTIVE, AND THERMALLY RESILIENT SILICON, GERMANIUM, OR SILICON-GERMANIUM ETCH-STOP
Granted: March 8, 2007
Application Number:
20070054460
A method and resulting etch-stop layer comprising a silicon-germanium layer and a dopant layer within the silicon-germanium layer. The silicon-germanium layer is comprised of less than about 70% germanium and contains one or more dopant elements selected from the group consisting of boron and carbon. The dopant layer has one or more of the dopant elements and an FWHM thickness value of less than 50 nanometers.
Device for converting a continuous supply voltage into a continuous output voltage and corresponding electronic circuit
Granted: March 1, 2007
Application Number:
20070046269
A device for converting a continuous supply voltage into a continuous output voltage includes at least one inductor accumulating energy during an accumulation time and delivering said accumulated energy during a discharge time, so that said output voltage has a value that is greater than or equal to that of said supply voltage. An oscillator controls said accumulation and discharge times, in which a period is equal to a sum of said accumulation time and said discharge time and a cyclic…
Device for comparing an input signal with a set value and corresponding electronic circuit
Granted: February 22, 2007
Application Number:
20070040546
This disclosure relates to a comparison device that receives an analogue input signal and a set value, and outputs a digital output signal. The device comprises a one-threshold comparator receiving the input signal and the set value, and the comparator generates a resultant signal that depends on the result of the comparison. Such a device comprises a sampler for sampling the resultant signal and a controller for blocking the sampler, after a switching of the input signal, as long as a…
Hysteresis comparator for input voltages and corresponding electronic circuit
Granted: February 22, 2007
Application Number:
20070040587
The disclosure relates to a hysteresis comparator of a first input voltage and a second input voltage. The comparator includes a first differential stage whose first and second inputs are respectively powered by the said first and second input voltages, and at least one second differential stage symmetrical to the said first differential stage. Two inputs of the said second differential stage are respectively powered by first and second reference voltages. At least one first current,…
