Mechanism for providing program breakpoints in a microcontroller with flash program memory
Granted: March 17, 2009
Patent Number:
7506206
A microcontroller is disclosed. The microcontroller includes a central processor unit (CPU) and a Flash program memory in communication with the CPU via an instruction bus. The microcontroller includes an on-chip debug (OCD) logic coupled to the CPU. The OCD logic containing logic that detects a zero opcode on an instruction bus between the CPU and the Flash program memory to provide a program breakpoint. This is an advantage over prior art in that any number of such breakpoints can be…
Measuring the internal clock speed of an integrated circuit
Granted: March 17, 2009
Patent Number:
7506228
A system and methods to transfer data between a testing interface and an IC. The system may include a synchronization subsystem to monitor the transitions of the test interface clock and/or IC clock to determine a clock adjustment appropriate to substantially synchronize the clocks. In certain implementations, a synchronization unit on an IC under test counts a predetermined number of transitions of an internal clock of an embedded device and generates a signal upon reaching a terminal…
Debugging system and method for use with software breakpoint
Granted: March 17, 2009
Patent Number:
7506205
Methods and systems are provided for debugging a program executing on a processor. In a first implementation, a processing system includes a processor configured for switching to a debug mode from a non-debug mode upon executing a software breakpoint. The system may include a program memory configured to hold instructions for a program, where the software breakpoint replaces at least one of the instructions. The system may also include an instruction replacement register separate from…
Method and apparatus for discharging a memory cell in a memory device after an erase operation
Granted: March 3, 2009
Patent Number:
7499334
A method and apparatus for discharging a memory cell in a memory device. In one implementation, the memory cell includes a capacitor having a first plate and a second plate, and the method includes initially discharging the first plate of the capacitor through a first discharge circuit and discharging the second plate of the capacitor through a second discharge circuit. After the initial discharge, the method further includes completely discharging the first plate of the capacitor and…
Integrated circuit structures having a boron- and carbon-doped etch-stop and methods, devices and systems related thereto
Granted: February 24, 2009
Patent Number:
7495250
A method for forming an etch-stop layer and a resulting structure fabricated therefrom. The etch-stop layer is a silicon-germanium layer having a ratio of silicon to germanium of about 50:1 or less, a boron layer formed within the silicon-germanium layer where the boron layer has a full-width half-maximum (FWHM) thickness value of less than 50 nanometers, and a carbon layer formed within the silicon-germanium layer where the carbon layer has an FWHM thickness value of less than 50…
Semiconductor article and method for manufacturing with reduced base resistance
Granted: February 10, 2009
Patent Number:
7488663
A method for manufacturing a semiconductor article and a semiconductor article is provided, wherein a base region of a first semiconductor material is applied, a silicide layer is applied above the base region, after the application of the silicide layer, an opening is created in the silicide layer by removing the silicide layer within the area of the opening, and after this, an emitter region is formed within the opening.
Arrangement for contacting an integrated circuit in a package
Granted: February 3, 2009
Patent Number:
7486093
An arrangement is provided for contacting an integrated circuit in a package by a contact plate arranged on a circuit carrier, wherein the package has contact locations on the contact plate side. In this context, the contact plate has contact vanes, which are formed such that they have a spring action directed normal to the circuit carrier and such that the contact vanes can be brought parallel to the circuit carrier by pressing the package against the contact vanes. The contact…
Radio controlled clock and method for retrieving time information from time signals
Granted: February 3, 2009
Patent Number:
7486657
Time information is retrieved from time signals transmitted by a transmitter and received by a receiver. The retrieval relies on the examination of at least one time portion (86, 87, 88) within a time frame. The time portion has a duration shorter than the duration of the time frame (80-82), to reduce processing operations. The examination checks whether an amplitude of the time signal changed within a time portion. The amplitude change either up or down is then evaluated for the…
Time efficient embedded EEPROM/processor control method
Granted: February 3, 2009
Patent Number:
7487287
In an embedded system with a processor and an EEPROM that provides an EEPROM BUSY signal if the EEPROM is in a write mode, a block-before-write subroutine is used to hold the processor before a write operation to the EEPROM. A detector circuit finds read functions that are to be mapped into the EEPROM address space and suspends code execution if an EEPROM BUSY bit is asserted and the EEPROM is the read target. Code execution by the processor and processor access to memories other than…
System and method for combining signals on a differential I/O link
Granted: January 27, 2009
Patent Number:
7482837
System and method for combining signals on a differential signal provided over a communication link. In one aspect, a system for providing a differential communication link includes a signal combination circuit that receives a data signal and a clock signal and outputs a modulated differential signal on a differential link, where the modulated differential signal includes a differential data signal having an offset modulated at a frequency of the clock signal. A receiving circuit…
Off-chip micro control and interface in a multichip integrated memory system
Granted: January 13, 2009
Patent Number:
7478213
A communication interface, coupling a controller device to one or more memory devices, provides a high-voltage reset interface. The high-voltage reset interface provides a high-voltage signal to reset the one or more memory devices. The high-voltage reset interface is implemented using a single interconnect line. The reset voltage signal is greater than a maximum voltage representing a high logic value. The communication interface may also include a bi-directional data and address…
Microprocessor access of operand stack as a register file using native instructions
Granted: January 13, 2009
Patent Number:
7478224
A combined native (RISC or CISC) microprocessor and stack (Java™) machine are constructed so that Java™ VM instructions can be executed in hardware. Most Java™ instructions are executed directly, while more complex Java™ instructions, such as those manipulating Java™ objects, are executed as native microcode. In order for native microcode instructions to access the Java™ operand stack, a Java™ operand stack pointer points to the register file location that is the current…
Reduced voltage pre-charge multiplexer
Granted: December 30, 2008
Patent Number:
7471132
An electronic device selects one of a plurality of input signals for coupling to an output channel. Individual pulldowns provide a separate pathway for each input, and are coupled to a common node which: is pre-charged to a voltage less than a system voltage. Each pulldown is coupled to a select line for gating an associated input signal.
Oscillator and method for operating an oscillator
Granted: December 30, 2008
Patent Number:
7471164
An oscillator is provided having an oscillator circuit including at least one oscillator circuit inductor and a first oscillator circuit capacitor, whereby the value of the first oscillator circuit capacitor is reversible by means of the first control voltages between different stages. The oscillator is characterized by a first control voltage source, which applies first control voltages with at least three stepwise different values to the first oscillator circuit capacitor. Preferably,…
Image sensor with rapid read cycle
Granted: December 30, 2008
Patent Number:
7471323
The invention proposes an image sensor comprising a picture capture matrix having N rows and K columns of image dots, a read register at the free end of the K columns. In order to improve the read speed of the matrix, the invention proposes that the horizontal transfer into the read register be continued even while the vertical signals for shifting from one row to the other are operative, without however continuing the horizontal transfer while the transfer gate between columns and…
Method and system for seamless mobility of mobile terminals in a wireless network
Granted: December 30, 2008
Patent Number:
7471656
Aspects for seamless mobility of mobile terminals in a wireless network are described. The aspects include utilizing a reassociation request from a mobile terminal to identify need for an internetwork handover of the mobile terminal roaming in a wireless local area network (WLAN), and performing a protocol sequence in an access point (AP) for the mobile terminal to handle the internetwork handover to ensure connectivity of the mobile terminal while roaming.
High-speed CMOS current mirror
Granted: December 16, 2008
Patent Number:
7466202
A CMOS current mirror is provided that includes a current input, an input transistor, whose conductivity path is located between the current input and a reference potential terminal, a current output, an output transistor, whose conductivity path is connected to the reference potential terminal and which supplies the current output with an output current, a gate node common for both transistors, and a supply potential terminal. The current mirror further includes a first additional…
Amplifier circuit
Granted: December 16, 2008
Patent Number:
7466206
Amplifier circuit for amplifying an input signal, having a vertically integrated cascode that has a collector semiconductor region of a collector, adjacent to the collector semiconductor region, a first base semiconductor region of a first base, a second base semiconductor region of a second base, an intermediate base semiconductor region adjoining both the first base semiconductor region and the second base semiconductor region, and an emitter semiconductor region of an emitter adjacent…
Sense amplifier for flash memory device
Granted: December 16, 2008
Patent Number:
7466613
A sense amplifier circuit comprises first and second cross-coupled inverters to produce a latch with first and second power supply nodes. The first latch power supply node couples a first power supply potential to the latch when the sense amplifier is operating in a read-out mode. The second latch power supply node couples a second power supply potential to the latch when the sense amplifier operates in the read-out mode. The first and second latch power supply nodes are further…
Beveled ergonomic image recorder with bent reading register
Granted: December 9, 2008
Patent Number:
7462807
The invention relates to small dimension image recorders, such as an image recorder, comprising a matrix of rows and columns of photosensitive points, arranged on a chip of a generally square or rectangular form with believed corners, characterised in comprising a reading register arranged at the base of the matrix. The register is bent to follow the bevelled corners of the chip and thus comprises a horizontal piece and two oblique pieces. The sensor further comprises means (ZIn) to…
