Circuit arrangement and method for supplying power to a transponder
Granted: May 19, 2009
Patent Number:
7535362
A circuit arrangement is provided for a power supply to a transponder including an antenna resonant circuit and a downstream rectifier circuit for receiving and for rectifying an electromagnetic signal, a charging capacitor connected downstream on the output side of the rectifier circuit to provide a first supply voltage, with a tuning circuit for tuning the antenna resonant circuit to its resonance frequency, and with an auxiliary voltage source, which is designed to provide a second…
High-voltage regulator system compatible with low-voltage technologies and corresponding electronic circuit
Granted: April 28, 2009
Patent Number:
7525294
A voltage regulator system is provided, which receives a first voltage and produces a regulated voltage. Such a device does not include any transistor supporting the first voltage, but does include transistors supporting at most a second voltage lower than the first voltage and includes division means, which include a first transistor connected in series with at least one second transistor, which division means receive the first voltage and generate the regulated voltage.
Apparatus and method to manage external voltage for semiconductor memory testing with serial interface
Granted: April 28, 2009
Patent Number:
7525856
A serial-interface flash memory device includes a data/address I/O pin and a clock input pin. A bidirectional buffer is coupled to the data/address I/O pin. A serial interface logic block including data direction control is coupled to the clock pin, the bidirectional buffer, to internal control logic, and to read-voltage and modify-voltage generators. A first switch is coupled to the read-voltage generator and the clock buffer and a second switch is coupled to the modify-voltage…
Method and system for creating self-aligned twin wells with co-planar surfaces in a semiconductor device
Granted: April 21, 2009
Patent Number:
7521312
A method and system for providing a twin well in a semiconductor device is described. The method and system include providing at least one interference layer and providing a first mask that covers a first portion of the semiconductor device and uncovers a second portion of the semiconductor device. The first and second portions of the semiconductor device are adjacent. The method and system also include implanting a first well in the second portion of the semiconductor device after the…
DMOS transistor with optimized periphery structure
Granted: April 21, 2009
Patent Number:
7521756
A lateral DMOS transistor is disclosed that includes a first region of a first conductivity type, which is surrounded on the sides by a second region of a second conductivity type, whereby a boundary line between both regions has opposite straight sections and curved sections linking the straight sections, and with a first dielectric structure, which serves as a field region and is embedded in the first region and surrounds a subregion of the first region. Whereby the first distance…
Differential amplifier and radio system with a differential amplifier
Granted: April 21, 2009
Patent Number:
7521996
A radio system for communication is provided that has a differential amplifier for amplifying a transmission frequency, particularly 2.4 GHz, wherein the differential amplifier has a first inductor, which is magnetically coupled to a second inductor, and a capacitor. The capacitor, the first inductor, and the second inductor are wired into a resonant circuit in such a way that the resonant circuit has a common-mode impedance for a common-mode signal and a push-pull impedance, different…
Biasing current to speed up current mirror settling time
Granted: April 21, 2009
Patent Number:
7522002
A current mirror circuit includes a first current-mirror transistor coupled to a second current-mirror transistor. A load is coupled to the second current-mirror transistor. A first current source is coupled to the first current-mirror transistor to cause a bias current to flow through the first current-mirror transistor and a second current source is coupled to the second current-mirror transistor and in parallel with the load to shunt the bias current away from the load.
Method and system for reducing soft-writing in a multi-level flash memory
Granted: April 21, 2009
Patent Number:
7522455
A system and method for reducing soft-writing in a multilevel flash memory during read or verify includes a memory cell. A first and second reference cells are coupled to the memory cell and are configured to receive a first and a second voltage. A current comparison circuit is coupled to the first and second reference cells and to the memory cell and is configured to compare current flow through the memory cell with current flow through the first and second reference cells, and to…
Sense amplifier with stages to reduce capacitance mismatch in current mirror load
Granted: April 21, 2009
Patent Number:
7522463
A sense amplifier circuit for reading the state of memory cells. In one aspect of the invention, the sense amplifier circuit includes a first stage receiving a cell current derived from the memory cell and a reference current derived from a reference cell, and a second stage receiving the cell current and the reference current. A comparator, coupled to the first stage and the second stage, provides an output indicative of the state of the memory cell based on a difference of the voltages…
Circuit arrangement for processing satellite signals
Granted: April 14, 2009
Patent Number:
7518549
A circuit arrangement is provided for processing satellite signals comprising a first circuit part, which is made as a processor for computing position and/or speed signals from satellite signals, a second circuit part, which is made as a real-time clock to provide a time signal, at least two voltage sources, which are provided to supply at least one circuit part, and switching means, which are provided for switching the supply of at least one circuit part between the first voltage…
Method and apparatus to test the power-on-reset trip point of an integrated circuit
Granted: April 14, 2009
Patent Number:
7519486
Circuitry for testing a power-on-reset circuit in an integrated circuit includes a high-voltage detector coupled to a first I/O pad of the integrated circuit. A power-on-reset circuit in the integrated circuit has an output coupled to a driver circuit that is powered by the high-voltage. A second I/O pad of the integrated circuit is coupled to the output of the driver circuit. The driver circuit may be enabled by a signal provided on a third I/O pad of the integrated circuit.
Device for converting a continuous supply voltage into a continuous output voltage and corresponding electronic circuit
Granted: April 14, 2009
Patent Number:
7518345
A device for converting a continuous supply voltage into a continuous output voltage includes at least one inductor accumulating energy during an accumulation time and delivering said accumulated energy during a discharge time, so that said output voltage has a value that is greater than or equal to that of said supply voltage. An oscillator controls said accumulation and discharge times, in which a period is equal to a sum of said accumulation time and said discharge time and a cyclic…
Capacitive sensor
Granted: April 7, 2009
Patent Number:
7515140
A capacitive sensor for detecting the presence of an object adjacent a panel is described. The sensor comprises an electrically conducting sensor element coupled to a capacitance measurement circuit. In use, the capacitive sensor is mounted with the sensor element adjacent an underside of the panel. The sensor element includes a flared portion which deforms when pressed against the panel to provide an extended contact area between the sensor element and the panel. When a user touches an…
Column redundancy RAM for dynamic bit replacement in FLASH memory
Granted: April 7, 2009
Patent Number:
7515469
A column redundancy system for a non-volatile memory includes a separate companion controller chip that includes a column redundancy RAM memory array for storing addresses of defective non-volatile memory cells. Column redundancy match logic provides a match output signal corresponding to a match of a particular user input address for the non-volatile memory with the address of a defective non-volatile memory cell, the collection of said addresses stored in the column redundancy RAM…
Electronic driver device for an external load for which the slew rate of the output signal is independent of the external load capacity and the corresponding integrated component
Granted: March 31, 2009
Patent Number:
7511541
This disclosure relates to an electronic driver device for an external load to which an input signal is applied at its input and that produces an output signal to the external load from its output. Such an electronic driver device includes elements that reduce dependence of the slew rate of the output signal on the external load capacitance.
Circuit to control voltage ramp rate
Granted: March 31, 2009
Patent Number:
7512008
A programming circuit and method to apply a controlled or predetermined voltage pulse for charge transfer to or from the floating gate of a non-volatile memory cell in an incremental manner to control the overall voltage across the gate oxide. Voltage above a transfer threshold voltage, such as above a tunneling threshold voltage, is applied in a stepwise charge transfer manner to or from the floating gate up to a voltage limit that is below the thin oxide damage threshold. Controlling…
Frequency modulator
Granted: March 24, 2009
Patent Number:
7508276
A frequency modulator is provided for generating an output signal with a frequency that is a function of a modulation signal, wherein the modulation signal can assume N?2 different discrete modulation values, and a predetermined frequency value of the output signal is associated with each modulation value, containing: a) a closed phase locked loop with a loop filter for providing a first control voltage, with a voltage controlled oscillator for generating the output signal, and with a…
Integrated protection circuit
Granted: March 17, 2009
Patent Number:
7503775
An integrated protection circuit is provided to protect an integrated component against an electrostatic discharge with a conductive structure between the integrated component and a housing terminal, whereby two substantially parallel conductive sections of the conductive structure guide the electrostatic discharge in a preferential direction by inductive coupling.
High-voltage field-effect transistor
Granted: March 17, 2009
Patent Number:
7504692
High-voltage field-effect transistor is provided that includes a drain terminal, a source terminal, a body terminal, and a gate terminal. A gate oxide and a gate electrode, adjacent to the gate oxide, is connected to the gate terminal. A drain semiconductor region of a first conductivity type is connected to the drain terminal. A source semiconductor region of a first conductivity type is connected to the source terminal. A body terminal semiconductor region of a second conductivity type…
Programming pulse generator
Granted: March 17, 2009
Patent Number:
7505326
A signal generator circuit is configured to generate program signals for a memory array. The program signals are applied to word lines in the memory array, and have a transient state based on a coupling characteristic of the word lines and selector gates. The transient state is configured to minimize coupling between the word lines and the gates of the selectors so that a state of each selector remains unchanged during the transient state.
