Apparatus and method for reducing power consumption in electronic devices
Granted: October 14, 2008
Patent Number:
7437584
An apparatus and method for reducing power consumption in a programmable logic device (PLOD) having multiple logic blocks and macrocells. Power consumption is reduced by detecting programmable switch values in each macrocell and generating a clock control signal based on the switch values. The clock control signal controls a macrocell buffer used for compensating for distortion of clock signals inputted to the macrocell. The macrocell buffer is disabled if the clock signals are not being…
Dual CPU on-chip-debug low-gate-count architecture with real-time-data tracing
Granted: October 14, 2008
Patent Number:
7437616
The same microcontroller chip is configured to be either a Target version or a Link version of a microcontroller. The Target version runs an application program. To debug the Target microcontroller, the Link version of the microcontroller functions as a master debug microcontroller to the slave Target microcontroller running the application program. The Link microcontroller runs an interface translator program between a Host computer that runs a debug program, and the Target…
Complex domain floating point VLIW DSP with data/program bus multiplexer and microprocessor interface
Granted: October 14, 2008
Patent Number:
7437540
A system for digital signal processing, configured as a system on chip (SoC), combines a microprocessor core and digital signal processor (DSP) core with floating-point data processing capability. The DSP core can perform operations on floating-point data in a complex domain and is capable of producing real and imaginary arithmetic results simultaneously. This capability allows a single-cycle execution of, for example, FFT butterflies, complex domain simultaneous addition and…
Circuits to delay a signal from DDR-SDRAM memory device including an automatic phase error correction
Granted: October 7, 2008
Patent Number:
7433262
A method for delaying a control signal, includes receiving a clock signal, determining a number of delay elements required to generate a first delay equal to a target amount of the period of the clock signal, receiving a data signal having an edge generated at the same time as an edge of the control signal, determining a fraction number equal to the number of delay elements needed to generate a second delay for the data signal or the control signal to align their edges, divided by the…
Method and system for providing sensing circuitry in a multi-bank memory device
Granted: September 30, 2008
Patent Number:
7430150
A method and system for providing a multi-bank memory is described. The method and system include providing a plurality of banks. Each of the plurality of banks includes at least one array including a plurality of memory cells and analog sensing circuitry. The method and system further include providing common digital sensing circuitry coupled with the plurality of banks.
Charge pump regulator with multiple control options
Granted: September 23, 2008
Patent Number:
7427890
A voltage generator has a control circuit for controlling a dual-mode charge pump that has multiple control options provided by an optional pull down control signal and an optional stop control signal. The dual-mode charge pump is enabled by a high voltage enable control signal from a control circuit to provide a high-voltage output voltage level Vpp or a low-voltage output voltage level Vdd. A current sink transistor is coupled from the output of the dual-mode charge pump to a ground…
Writing to flash memory
Granted: September 23, 2008
Patent Number:
7428610
Writing to a page of flash memory may include receiving write commands that are substantially independent of an internal architecture of the flash memory. In certain embodiments, two operand flash commands are received at a flash controller from a remote controller. In various implementations, the writing process may further include translating each two-operand write command into architecture-dependent flash commands; executing the architecture-dependent flash commands to fill a page…
Method of forming pre-metal dielectric film on a semiconductor substrate including first layer of undoped oxide of high ozone:TEOS volume ratio and second layer of low ozone doped BPSG
Granted: September 16, 2008
Patent Number:
RE40507
A method of forming a pre-metal dielectric film having good as deposited gapfill characteristics, as well as good mobile-ion gettering capability. The method involves first depositing a layer of high-ozone undoped silicon dioxide film having a high ozone/TEOS volume ratio. Then, a low-ozone doped BPSG film is deposited over the high-ozone undoped silicon dioxide layer. The film layers are heat treated to densify the film, and then the top layer is planarized using known planarization…
Differential cascode amplifier
Granted: September 16, 2008
Patent Number:
7425865
A differential cascode amplifier is disclosed that includes in each branch two transistors connected to form a cascode circuit, and has a cross-compensation (neutralization) with at least one pair of capacitors for compensating a parasitic capacitance of a transistor of each branch, wherein in each case, one capacitor of the pair is equal to the parasitic capacitance of the transistor of the associated branch.
SONOS memory array with improved read disturb characteristic
Granted: September 9, 2008
Patent Number:
7423912
A PMOS non-volatile memory array using SONOS transistors having program and erase threshold voltages for representing digital logic states of zero and one and selected to optimize read disturb characteristics. The threshold voltages are linearly convergent and separated by at least 0.5 volts for a charge retention time of at least 10 years, with the threshold voltages defining a window wherein a read voltage for selected memory transistors can be held flat and not intersect the threshold…
Clock circuitry for DDR-SDRAM memory controller
Granted: September 9, 2008
Patent Number:
7423928
A circuit for providing a delayed clock signal to a synchronous memory controller controlling a synchronous memory device comprises logic delay circuitry for performing synchronous memory device read access, the logic delay circuitry generating delay interval information. A programmable delay line receives a clock signal and the delay interval information, the programmable delay line delaying the clock signal by the delay interval. A 2-input XOR gate receives both the clock signal and…
Self-aligned non-volatile memory cell
Granted: September 9, 2008
Patent Number:
RE40486
Disclosed is a self-aligned non-volatile memory cell including a small sidewall spacer electrically coupled and being located next to a main floating gate region. Both the small sidewall spacer and the main floating gate region are formed on a substrate and both form the floating gate of the non-volatile memory cell. Both are isolated electrically from the substrate by an oxide layer which is thinner between the small sidewall spacer and the substrate; and is thicker between the main…
Microcontroller interface with hall element
Granted: September 2, 2008
Patent Number:
7420349
A device controller system incorporates an inexpensive Hall element to detect motion of a brushless DC motor. A magnet, which is part of a motor rotor, passes by the Hall element producing a Hall voltage each rotation. The Hall voltage is coupled through an interface port to a comparator within a process controller. A microprocessor within the process controller calculates a control response based on a comparator output signal. The interface port is rapidly reconfigured to provide…
Adaptive gate voltage regulation
Granted: August 26, 2008
Patent Number:
7417904
A memory device generates a select voltage and an unselect voltage on bit lines and generates a bit line select voltage having a magnitude less than the unselect voltage so that the application of the bit line select voltage to a gate of a transistor receiving the select voltage causes the transistor to conduct, and the application of the bit line select voltage to a gate of a transistor receiving the unselect voltage biases the transistor off.
Method for forming a photonic band-gap structure and a device fabricated in accordance with such a method
Granted: August 26, 2008
Patent Number:
7418164
A device for application in the high frequency field and a method for forming a photonic band-gap structure are provided. The device being mountable on a primary substrate for forming the device. The device being formed by forming conformal coplanar waveguide metallizations on surface areas of two substrates, connecting the conformal coplanar waveguide metallizations of the two substrates, and structured back-etching of the two substrates, starting at surface areas of the two substrates…
Distributed amplifier topologies with improved gain bandwidth product
Granted: August 19, 2008
Patent Number:
7414477
A distributed amplifier is provided that includes an input network that simulates an input signal transmission line, and having an output network that simulates an output signal transmission line, and also having multiple unit cells with amplifying characteristics that are connected in parallel to one another between the input network and the output network, that amplify a signal propagating through the input network and feed it into the output network with a predetermined phase…
Erase verify method for NAND-type flash memories
Granted: August 19, 2008
Patent Number:
7414891
An erase-verify method for a NAND flash memory includes a serial double-step erase verify. A verify operation is performed on cells in the unit connected to even word lines by biasing all the even word lines at the read voltage value used in read mode, and by biasing all the odd word lines at the pass voltage value used in read mode of the selected unit. A verify operation is performed on the cells connected to odd word lines by biasing all the odd word lines at the read voltage value…
Process for automatically detecting the throughput of a network, particularly of the can bus type and for configuring with the detected throughput by transition analysis, and corresponding device
Granted: August 12, 2008
Patent Number:
7411913
A process for automatically detecting and configuring with the throughput of a network, in which a device: (a) goes into a listen mode; (b) obtains a triplet of successive transitions in a transmitted signal, the triplet delimiting first and second signal levels, one dominant and the other recessive; (c) measures the duration of each of the first and second levels; (d) as a function of the measured durations, obtains a new throughput configuration by determining values for parameters…
Method and testing apparatus for testing integrated circuits
Granted: August 5, 2008
Patent Number:
7408375
A method for testing integrated circuits comprises: generation of a change in an input signal of the integrated circuit, detection of a change in the output signal of the integrated circuit, the change triggered by the change in the input signal when a predetermined condition is satisfied, and a comparison of the detected output signal with at least one predetermined comparison criterion. Whereby, the predetermined condition is derived individually for each integrated circuit from a time…
Low-voltage single-layer polysilicon EEPROM memory cell
Granted: August 5, 2008
Patent Number:
7408812
The present invention is an electronic memory cell and a method for the cell's fabrication comprising a first transistor configured to be coupled to a bit line. The first transistor has an essentially zero voltage drop when activated and is configured to control an operation of the memory cell. A second transistor is configured to operate as a memory transistor and is coupled to the first transistor. The second transistor is further configured to be programmable with a voltage about…
