Bi-directional single wire interface
Granted: July 29, 2008
Patent Number:
7406100
A single-wire, bi-directional communication protocol is provided in which the sending device transmits its clock frequency and its bit transmission period and data through a predefined waveform pattern or “learning sequence” that is recognizable by the receiving device and in a period of time, as measured in number of sending clock cycles, that is known to the receiving device. By clocking the full length of the predefined waveform pattern using its own internal clock, the receiving…
Standard CMOS low-noise high PSRR low drop-out regulator with new dynamic compensation
Granted: July 29, 2008
Patent Number:
7405546
A voltage regulator circuit has a first amplifier stage with input and output terminals, a feedback terminal, a pole-inducing transistor, and a compensating network coupled to the output terminal. A second amplifier stage has an input coupled to the first amplifier output, first and second current mirrors, and a pass transistor.
Non-volatile transistor memory array incorporating read-only elements with single mask set
Granted: July 22, 2008
Patent Number:
7402482
A memory array has memory elements of identical topology or footprint arranged in rows and columns. Some of the memory elements are EEPROM cells and other memory elements are read only memory cells but all are made using a mask set having the same length and width dimensions. In the mask set for EEPROMs a principal mask is used for formation of a depletion implant. In the case of one type of read-only memory element, this mask is mainly blocked, leading to formation of a transistor with…
Electrostatic discharge (ESD) protection structure and a circuit using the same
Granted: July 22, 2008
Patent Number:
7402846
An electrostatic discharge (ESD) protection structure is disclosed. The ESD protection structure includes an active device. The active device includes a plurality of drains. Each of the drains has a contact row and at least one body contact row. The at least one body contact row is located on the active device in a manner to reduce the amount of voltage required for triggering the ESD protection structure.
Method and system for managing address bits during buffered program operations in a memory device
Granted: July 22, 2008
Patent Number:
7404049
A method and system for managing a buffered program operation for plurality of words is described. In one aspect, the method and system include providing an internal buffer including a plurality of locations and at least one bit location for the plurality of locations. Each of the words is stored in a location of the plurality of locations. The words are associated with internal address bits for the locations. At least one of the internal address bits is at least one group address bit…
Method for integrating an electronic component or similar into a substrate
Granted: July 8, 2008
Patent Number:
7396739
A method for integrating an electronic component or the like into a substrate includes following process steps: formation of a dielectric insulating layer on the front side of a substrate; complete back-etching of an area of the substrate from the back of the substrate to form a cavity; formation of a photoresistive layer with a homogeneous thickness over the back of the substrate; placement of an electronic component on the photoresistive layer formed in the cavity for adhesion of the…
Method for integration of three bipolar transistors in a semiconductor body, multilayer component, and semiconductor arrangement
Granted: July 8, 2008
Patent Number:
7397109
A method for integrating three bipolar transistors into a semiconductor body, multilayer component, and semiconductor arrangement is provided. A tendency toward thyristor-like behavior of the multilayer semiconductor arrangements with the three bipolar transistors is suppressed with the aid of a heterojunction. The high frequency characteristics and the blocking capability of the circuit of the three bipolar transistors is made more flexible, while the capability of an input signal to…
Channel discharging after erasing flash memory devices
Granted: July 8, 2008
Patent Number:
7397699
A post-erase channel clearing procedure for double well, floating gate, non-volatile memory cells. The channel is cleared of charged particles coming from the floating gate after an erase operation in two steps. In the first step the charged particles are pushed into an upper substrate well below the floating gate but not allowed into a deeper well of opposite conductivity type relative to the upper well. After a brief time, T, the charged particles are pushed by a bias voltage into the…
Fast read port for register file
Granted: July 8, 2008
Patent Number:
7397723
Separate read and write ports in a memory system allow simultaneous access to a memory cell array by read and write operations. A single cycle operation of a central processing unit coupled to a memory array depends on a memory access capability providing simultaneous reading and writing to different locations. A pair of pull-down transistor stacks connected to memory cell latch loops allows a single selected pull-down stack of the pair to toggle a memory cell latch loop to a desired…
Fast analogue-to-digital converter
Granted: July 1, 2008
Patent Number:
7394421
The invention relates to fast analogue-to-digital converters having differential inputs and a parallel structure, comprising at least one network of N series resistors with value r and one network of N comparators. The series resistor network receives a reference voltage and is traversed by a fixed current Io and the row i (i varying from 1 to N) comparator essentially comprises a dual differential amplifier with four inputs; two inputs receive a differential voltage VS?VN to be…
Secure memory device for smart cards
Granted: July 1, 2008
Patent Number:
7395435
A secure memory device which can be used for multi-application smart cards for secure identification in data transfer, or for component verification in a computer system, without the requirement of an internal microprocessor. The secure memory device features a dual authentication protocol in which the memory and host authenticate each other. The secure memory device also includes an encrypted password feature, as well as using stream encryption to encrypt the data.
Flat top optical filtering component
Granted: July 1, 2008
Patent Number:
7394986
The invention relates to wavelength-selective optical filters for allowing light of a narrow optical spectral band, centered around a wavelength (?c) to pass through them, while reflecting the wavelengths lying outside this band. According to the invention, the transfer function (T1,2(?)) of the component is defined by multiplying two transfer functions of spectrally offset Fabry-Perot filters.
Method of producing a digital fingerprint sensor and the corresponding sensor
Granted: July 1, 2008
Patent Number:
7393711
An embodiment of the present invention related to fingerprint sensors is described. The sensor comprises an integrated-circuit chip having a sensitive surface, a substrate provided with electrical connections and wire-bonding wires connecting the chip to the electrical connections. The sensor further includes a molded protective resin at least partly covering the substrate and the chip and completely encapsulating the wire-bonding wires. The resin forms, on at least one side of the chip…
Method for simultaneous fabrication of a nanocrystal and non-nanocrystal device
Granted: June 24, 2008
Patent Number:
7391081
A method of simultaneously fabricating at least two semiconductor devices, at least bone of which is a nanocrystal memory and at least one of which is a non-nanocrystal semiconductor device. A nanocrystal layer is formed over an oxide layer of the at least two semiconductor devices being fabricated. The nanocrystal layer is removed from at least one portion of the substrate corresponding to the at least one non-nanocrystal device being fabricated. A polycrystalline gate is formed for…
Comparison circuit for analog/digital converter
Granted: June 24, 2008
Patent Number:
7391352
The invention pertains to a comparison circuit for an analog/digital converter. In order to reduce the effect of the offset voltages of the various comparators of the comparison circuit, voltage followers and a resistor network delivering at its outputs, mean voltages that are the average of those present on outputs of the comparators are linked downstream of the outputs of the comparators.
Efficient multiplication sequence for large integer operands wider than the multiplier hardware
Granted: June 24, 2008
Patent Number:
7392276
A method of operating a multiplication circuit to perform multiply-accumulate operations on multi-word operands is characterized by an operations sequencer that is programmed to direct the transfer of operand segments between RAM and internal data registers in a specified sequence. The sequence processes groups of two adjacent result word-weights (columns), with the multiply cycles within a group proceeding in a zigzag fashion by alternating columns with steadily increasing or decreasing…
Method and apparatus for determining stuck-at fault locations in cell chains using scan chains
Granted: June 24, 2008
Patent Number:
7392448
Methods and apparatus are provided for testing digital circuits. In one implementation, a scan chain test structure is provided that includes a cell chain, a first scan chain, and a second scan chain. The first scan chain is operable to test digital circuitry within a first portion of the cell chain, and the second scan chain is operable to test digital circuitry within a second portion of the cell chain. The first scan chain is further operable to test digital circuitry within the…
Asynchronous arbitration device and microcontroller comprising such an arbitration device
Granted: June 17, 2008
Patent Number:
7389373
An arbitration device is provided, which is designed to be connected between, on the one hand, a first and a second module and, on the other hand, storing means forming a memory workspace. This arbitration device includes a detector for detecting one or more requests coming, concurrently or not, from the first and second modules, for the purpose of accessing the memory workspace.
Low resistance integrated MOS structure
Granted: June 10, 2008
Patent Number:
7385263
The present invention is related to a metal-oxide semiconductor field-effect transistor (MOSFET) having a symmetrical layout such that the resistance between drains and sources is reduced, thereby reducing power dissipation. Drain pads, source pads, and gates are placed on the MOSFET such that the distances between drains, sources, and gates are optimized to reduce resistance and power dissipation. The gates may be arranged in a trapezoidal arrangement in order to maximize a ratio of the…
Sensor manufacture with data storage
Granted: June 10, 2008
Patent Number:
7385381
A biometric sensing device includes a sensor manufacture for sensing a biometric stimulus. The sensor manufacture is also configured to persistently store data electronically, such as security data.
