Cavium Profile

Cavium Patent Grants

Method and apparatus for virtualization

Patent Number 9823868 - November 21, 2017

A virtual system on chip (VSoC) is an implementation of a machine that allows for sharing of underlying physical machine resources between…

Memory management for finite automata processing

Patent Number 9823895 - November 21, 2017

Matching at least one regular expression pattern in an input stream may be optimized by initializing a search context in a run stack based on…

Apparatus and method for parallel CRC units for variably-sized data frames

Patent Number 9823960 - November 21, 2017

A cyclic redundancy check (CRC) device configured to support parallel calculation of a CRC value for a data frame comprises a plurality of CRC…

Bypass FIFO for multiple virtual channels

Patent Number 9824058 - November 21, 2017

A group of low-level FIFOs may be logically bound together to form a super-FIFO. The super-FIFO may treat each low-level FIFO as a storage…

Method and apparatus for discarding unused points from constellation mapping rule using transceiver processing hardware (“TPH”)

Patent Number 9825799 - November 21, 2017

An aspect of present invention discloses a transceiver processing hardware (“TPH”) which is configured to process wireless information…

Cavium Patent Applications

METHOD AND APPARATUS FOR EFFICIENT AND FLEXIBLE DIRECT MEMORY ACCESS

Application Number 20170329731 - November 16, 2017

Method and system embodying the method for a direct memory access between a data storage and a data processing device via one or more direct…

Methods and Apparatus for Frequency Offset Estimation

Application Number 20170331664 - November 16, 2017

Methods and apparatus for frequency offset estimation are disclosed. In an exemplary embodiment, a method includes determining a demodulation…

METHOD AND APPARATUS FOR SHARED MULTI-PORT MEMORY ACCESS

Application Number 20170301382 - October 19, 2017

Method and system embodying the method for a general address transformation for an access to a shared memory comprising at least one tile and…

METHODS AND APPARATUS FOR PROVIDING AN FFT ENGINE USING A RECONFIGURABLE SINGLE DELAY FEEDBACK ARCHITECTURE

Application Number 20170220523 - August 3, 2017

Methods and apparatus for providing an FFT engine using a reconfigurable single delay feedback architecture. In one aspect, an apparatus…

METHODS AND APPARATUS FOR A VECTOR MEMORY SUBSYSTEM FOR USE WITH A PROGRAMMABLE MIXED-RADIX DFT/IDFT PROCESSOR

Application Number 20170192935 - July 6, 2017

A vector memory subsystem for use with a programmable mix-radix vector processor (“PVP”) capable of calculating discrete Fourier transform…