Methods and apparatus for frequency offset estimation
Granted: August 17, 2021
Patent Number:
11095491
Methods and apparatus for frequency offset estimation are disclosed. In an exemplary embodiment, a method includes determining a demodulation reference signal (DMRS) frequency offset estimate from DMRS symbols in a received signal, and determining a cyclic prefix (CP) frequency offset estimate from cyclic prefix values in the received signal. The method also includes combining the DMRS and CP frequency offset estimates to determine a final frequency offset estimate. In an exemplary…
Method and apparatus for efficient and flexible direct memory access
Granted: May 18, 2021
Patent Number:
11010318
Method and system embodying the method for a direct memory access between a data storage and a data processing device via one or more direct memory access units, comprising transferring data between the data storage and a first direct memory access engine of a respective one or more direct memory access units and providing the data for a second direct memory access engine of the respective one or more direct memory access units; and transferring the data provided by the first direct…
Methods and apparatus for control channel detection in an uplink shared channel
Granted: May 4, 2021
Patent Number:
10999826
Methods and apparatus for channel detection in an uplink shared control channel. In an exemplary embodiment, a method includes generating soft-combined bit streams for an acknowledgement (ACK) indicator, rank indicator (RI), and channel quality indicator (CQI) received in an uplink shared channel. The method also includes decoding the ACK, RI, and CQI soft-combined bit streams to generate Top-M decoded bit streams for each indicator, and generating Top-Q symbols for each indicator from…
Methods and apparatus for providing a demapping system to demap uplink transmissions
Granted: March 16, 2021
Patent Number:
10952187
Methods and apparatus for providing a demapping system to demap uplink transmissions. In an embodiment, a method is provided that includes detecting a processing type associated with a received uplink transmission, and when the detected processing type is a first processing type then performing the following operations: removing resource elements containing reference signals from the uplink transmission; layer demapping remaining resource elements of the uplink transmission into two or…
Methods and apparatus for dynamic acknowledgement list selection in detection of uplink control channel formats
Granted: January 12, 2021
Patent Number:
10892876
Methods and apparatus for dynamic acknowledgement list selection in detection of uplink control channel formats. In an exemplary embodiment, an apparatus includes a dynamic acknowledgement (ACK) list allocation circuit that generates a dynamic ACK list that includes one or two most likely ACK candidates, and a top-Q candidate CQI bits detector that dynamically allocates a detection branch to each of the one or two most likely ACK candidates to detect top-Q candidate CQI bits. The…
Method and apparatus for a vector memory subsystem for use with a programmable mixed-radix DFT/IDFT processor
Granted: January 12, 2021
Patent Number:
10891256
A vector memory subsystem for use with a programmable mix-radix vector processor (“PVP”) capable of calculating discrete Fourier transform (“DFT/IDFT”) values. In an exemplary embodiment, an apparatus includes a vector memory bank and a vector memory system (VMS) that generates input memory addresses that are used to store input data into the vector memory bank. The VMS also generates output memory addresses that are used to unload vector data from the memory banks. The input…
Methods and apparatus for job scheduling in a programmable mixed-radix DFT/IDFT processor
Granted: December 29, 2020
Patent Number:
10878060
Methods and apparatus for job scheduling in a programmable mixed-radix DFT/IDFT processor. In an exemplary embodiment, a method includes receiving a plurality of discrete Fourier transform (DFT) jobs. Each job identifies a computation of a DFT of a particular point size. The method also includes bundling selected jobs having a selected point size into a mega-job, and identifying a radix factorization for the selected point size. The radix factorization includes one or more stages and…
Methods and apparatus for two-stage ACK/DTX detection
Granted: September 8, 2020
Patent Number:
10772153
Methods and apparatus for two-stage ACK/DTX detection. In an embodiment, a method includes determining a first stage DTX value from bit-domain correlation values, and determining a second stage DTX value from symbol domain correlation values generated from candidate ACK bits. The method also includes determining a DTX decision based on the first stage DTX value and the second stage DTX value.
Methods and apparatus for twiddle factor generation for use with a programmable mixed-radix DFT/IDFT processor
Granted: September 8, 2020
Patent Number:
10771947
Twiddle factor generation for use with a programmable mix-radix vector processor (“PVP”) capable of calculating discrete Fourier transform (“DFT/IDFT”) values. In an exemplary embodiment, an apparatus includes look-up table logic that receives twiddle control factors and outputs a selected twiddle factor scaler value (TFSV), a base vector generator that generates a base vector values based on the selected TFSV, and a twiddle column generator that generates a twiddle vector from…
Apparatus and method of generating lookups and making decisions for packet modifying and forwarding in a software-defined network engine
Granted: August 18, 2020
Patent Number:
10749800
Embodiments of the present invention relate to a Lookup and Decision Engine (LDE) for generating lookup keys for input tokens and modifying the input tokens based on contents of lookup results. The input tokens are parsed from network packet headers by a Parser, and the tokens are then modified by the LDE. The modified tokens guide how corresponding network packets will be modified or forwarded by other components in a software-defined networking (SDN) system. The design of the LDE is…
Methods and systems for load balancing in network devices
Granted: August 11, 2020
Patent Number:
10740155
Methods and systems for network devices are provided. One method includes receiving a frame by a network device communicating with a computing device via a peripheral link, the network device receiving the frame via a network connection; using one or more frame header fields to generate a frame context by the network device; determining if a processor of the network device is processing another frame with the same frame context; assigning the frame context to a first processor of the…
Method and apparatus for load balancing of jobs scheduled for processing
Granted: July 14, 2020
Patent Number:
10713089
Method and system embodying the method for load balancing of scheduled jobs among a plurality of engines encompassing determining a number of cluster credits for each of a plurality of clusters that comprise at least one engine capable of processing a scheduled job; determining a number of engine credits for each of the plurality of engines comprising each of the at least one engine in accordance with a number of jobs assigned to each of the plurality of engines; evaluating the…
VOQ-based network switch architecture using multi-stage arbitration fabric scheduler
Granted: June 30, 2020
Patent Number:
10700998
A network switch capable of supporting cut-though switching and interface channelization with enhanced system performance. The network switch includes a plurality of ingress tiles, each tile including a virtual output queue (VOQ) scheduler operable to submit schedule requests to a fabric scheduler. Data is requested in unit of quantum which may aggregate multiple packets, which reduces schedule latency. Each request is associated with a start-of-quantum (SoR) state or a middle-of-quantum…
Method and apparatus for providing a low latency transmission system using adaptive buffering estimation
Granted: June 16, 2020
Patent Number:
10686704
One aspect of the present invention discloses a network system capable of transmitting and processing audio video (“A/V”) data with enhanced quality of service (“QoS”). The network system includes a transmitter, a transmission channel, an adjustable decoder buffer, and a decoder. The transmitter contains an encoder able to encode A/V data in accordance with encoding bit rate recommendation from SQoS and packets loss notifications. The transmission channel, in one example,…
Compressing like magnitude partial products in multiply accumulation
Granted: June 16, 2020
Patent Number:
10684825
An ALU capable of generating a multiply accumulation by compressing like-magnitude partial products. Given N pairs of multiplier and multiplicand, Booth encoding is used to encode the multipliers into M digits, and M partial products are produced for each pair of with each partial product in a smaller precision than a final product. The partial products resulting from the same encoded multiplier digit position, are summed across all the multiplies to produce a summed partial product. In…
Method and apparatus for analytics in a network switch
Granted: June 9, 2020
Patent Number:
10680957
Embodiments of the present invention relate to a centralized network analytic device, the centralized network analytic device efficiently uses on-chip memory to flexibly perform counting, traffic rate monitoring and flow sampling. The device includes a pool of memory that is shared by all cores and packet processing stages of each core. The counting, the monitoring and the sampling are all defined through software allowing for greater flexibility and efficient analytics in the device. In…
Apparatus and a method of detecting errors on registers
Granted: May 19, 2020
Patent Number:
10656992
An error detection circuit on a semiconductor chip detects whether soft errors have affected flip-flop implemented registers on the semiconductor chip. A signature of these flip-flop implemented registers on the semiconductor chip is periodically captured. The signature allows for the integrity of the flip-flop implemented registers to be constantly monitored. A soft error occurring on any of the flip-flop implemented registers can be immediately detected. In response to the detection,…
Methods and apparatus for sub-block based architecture of cholesky decomposition and channel whitening
Granted: May 12, 2020
Patent Number:
10651951
Methods and apparatus for sub-block based architecture of Cholesky decomposition and channel whitening. In an exemplary embodiment, an apparatus is provided that parallel processes sub-block matrices (R00, R10, and R11) of a covariance matrix (R) to determine a whitening coefficient matrix (W). The apparatus includes a first LDL coefficient calculator that calculates a first whitening matrix W00, lower triangle matrix L00, and diagonal matrix D00 from the sub-block matrix R00, a first…
External DQS bi-directional loopback with use of feed forward equalization path
Granted: May 12, 2020
Patent Number:
10649025
A byte lane of an integrated circuit including two data strobe loopback paths that allow external test signals to flow in and out of the integrated circuit through data strobe pins in two opposite directions. The integrated circuit includes a Feed Forward Equalization (FFE) path configured to send FFE signals output from the FFE logic via a transmitter set to a first data strobe interface during a normal operation. In a loopback test mode operation, a test signal can be supplied from a…
Virtualized network interface for lockdown and overlay of data in transmitted packets
Granted: May 5, 2020
Patent Number:
10644998
A method and a system embodying the method for data lockdown and data overlay in a packet to be transmitted, comprising providing a first and a second masks comprising one or more position(s) and a data value at each of the one or more position(s); aligning the masks with the packet; comparing the data value at each of the one or more position(s) in the first mask with the data value at the one or more aligned position(s) in the packet; optionally replacing a data value at each of the…
