SYSTEM AND METHOD FOR ENABLING ACCESS TO A PROTECTED HARDWARE RESOURCE
Granted: February 2, 2012
Application Number:
20120027199
Systems and methods are disclosed for enabling access to a protected hardware resource. A hardware component includes at least one protected hardware resource. A unique hardware ID and a unique cryptographically secure or randomly generated enable value (EV) are integrated in the hardware component at the time of manufacturing. At run-time, special software generates or receives from an external source an enable register (ER) value and a comparison is made with the stored enable value.…
System and Method for Secure Device Key Storage
Granted: January 12, 2012
Application Number:
20120011373
Disclosed are systems and methods for protecting secret device keys, such as High-bandwidth Digital Content Protection (HDCP) device keys. Instead of storing secret device keys in the plain, a security algorithm and one or more protection keys are stored on the device. The security algorithm is applied to the secret device keys and the one or more protection keys to produce encrypted secret device keys. The encrypted secret device keys are then stored either on chip or off-chip.
SYSTEM AND METHOD FOR TRANSMITTING MULTIMEDIA STREAM
Granted: November 10, 2011
Application Number:
20110274156
Systems and methods for transmitting a multimedia stream are disclosed. A transmitter encodes audio data, video data, and control information received from a source and transmits over a network the different types of data to a receiver coupled to a display. The systems and methods utilize different network queues for the different types of traffic in order to account for differences in quality of service (QoS) parameters. The systems and methods adaptively adjust encoding and…
SYSTEM AND METHOD FOR LOW-LATENCY MULTIMEDIA STREAMING
Granted: November 10, 2011
Application Number:
20110276710
Systems and methods for transmitting a multimedia stream over a communication link on a network are disclosed. The systems and methods adaptively adjust encoding parameters based on monitoring changing conditions of the network. A transmitter includes an adaptive-rate encoder that adaptively adjusts a video encoding bit rate in response to changing conditions of the communication link. The encoder maintains tight rate control by utilizing slice processing and sub-frame rate adaptation,…
METHOD AND APPARATUS FOR A VIRTUAL SYSTEM ON CHIP
Granted: November 3, 2011
Application Number:
20110271277
A virtual system on chip (VSoC) is an implementation of a machine that allows for sharing of underlying physical machine resources between different virtual systems. A method or corresponding apparatus of the present invention relates to a device that includes a plurality of virtual systems on chip and a configuring unit. The configuring unit is arranged to configure resources on the device for the plurality of virtual systems on chip as a function of an identification tag assigned to…
METHOD AND APPARATUS FOR POWER CONTROL
Granted: July 28, 2011
Application Number:
20110185203
Embodiments of the present invention relate to limiting maximum power dissipation occurred in a processor. Therefore, when an application that requires excessive amounts of power is being executed, the execution of the application may be prevented to reduce dissipated or consumed power. Example embodiments may stall the issue or execution of instructions by the processor, allowing software or hardware to reduce the power of an application by imposing a decrease in the performance of the…
Multiple core Session Initiation Protocol (SIP)
Granted: May 27, 2010
Application Number:
20100131658
A Session Initiation Protocol (SIP) proxy server including a multi-core central processing unit (CPU) is presented. The multi-core CPU includes a receiving core dedicated to pre-SIP message processing. The pre-SIP message processing may include message retrieval, header and payload parsing, and Call-ID hashing. The Call-ID hashing is used to determine a post-SIP processing core designated to process messages between particular user pair. The pre-SIP and post-SIP configuration allows for…
Deterministic Finite Automata Graph Traversal with Nodal Bit Mapping
Granted: May 6, 2010
Application Number:
20100114973
An apparatus, and corresponding method, for generating a graph used in performing a search for a match of at least one expression in an input stream is presented. The graph includes a number of interconnected nodes connected solely by valid arcs. A valid arc may also include a nodal bit map including structural information of a node to which the valid arc points to. A walker process may utilize the nodal bit map to determine if a memory access is necessary. The nodal bit map reduces the…
Method and apparatus for content based searching
Granted: February 25, 2010
Application Number:
20100050177
The scheduling of multiple request to be processed by a number of deterministic finite automata-based graph thread engine (DTE) workstations is processed by a novel scheduler. The scheduler may select an entry from an instruction in a content search apparatus. Using attribute information from the selected entry, the scheduler may thereafter analyze a dynamic scheduling table to obtain placement information. The scheduler may determine an assignment of the entry, using the placement…
METHOD AND APPARATUS FOR REDUCING HOST OVERHEAD IN A SOCKET SERVER IMPLEMENTATION
Granted: January 28, 2010
Application Number:
20100023626
A network application executing on a host system provides a list of application buffers in host memory stored in a queue to a network services processor coupled to the host system. The application buffers are used for storing data transferred on a socket established between the network application and a remote network application executing in a remote host system. Using the application buffers, data received by the network services processor over the network is transferred between the…
SECURE SOFTWARE AND HARDWARE ASSOCIATION TECHNIQUE
Granted: August 27, 2009
Application Number:
20090217054
In an embodiment, authenticated hardware and authenticated software are cryptographically binded using symmetric and asymmetric cryptography. Cryptographically binding the hardware and software ensures that original equipment manufacturer (OEM) hardware will only run OEM software. Cryptographically binding the hardware and software protects the OEM binary code so it will only run on the OEM hardware and cannot be replicated or altered to operate on unauthorized hardware. This…
Deterministic finite automata (DFA) graph compression
Granted: May 28, 2009
Application Number:
20090138494
An apparatus, and corresponding method, for generating a graph used in performing a search for a match of at least one expression in an input stream is presented. The graph includes a number of interconnected nodes connected solely by valid arcs. A valid arc of a current node represents a character match in an expression of a character associated with the current node. Arcs which are not valid may be pruned. Non-valid arcs may include arcs which point back to a designated node(s), or…
Intelligent graph walking
Granted: May 7, 2009
Application Number:
20090119399
An apparatus, and corresponding method, for performing a search for a match of at least one expression in an input stream is presented. A graph including a number of interconnected nodes is generated. A compiler may assign at least one starting node and at least one ending node. The starting node includes a location table with node position information of an ending node and a sub-string value associated with the ending node. Using the node position information and a string comparison…
Graph caching
Granted: May 7, 2009
Application Number:
20090119279
In a method and apparatus for analyzing nodes of a Deterministic Finite Automata (DFA), an accessibility ranking, based on a DFA graph geometrical configuration, may be determined in order to determine cacheable portions of the DFA graph in order to reduce the number of external memory accesses. A walker process may be configured to walk the graph in a graph cache as well as main memory. The graph may be generated in a manner allowing each arc to include information if the node it is…
Store instruction ordering for multi-core processor
Granted: May 4, 2006
Application Number:
20060095741
A method and apparatus for minimizing stalls in a pipelined processor is provided. Instructions in an out-of-order instruction scheduler are executed in order without stalling the pipeline by sending store data to external memory through an ordering queue.
Packet queuing, scheduling and ordering
Granted: March 16, 2006
Application Number:
20060056406
A method and apparatus for ordering, synchronizing and scheduling work in a multi-core network services processor is provided. Each piece of work is identified by a tag that indicates how the work is to be synchronized and ordered. Throughput is increased by processing work having different tags in parallel on different processor cores. Packet processing can be broken up into different phases, each phase having a different tag dependent on ordering and synchronization constraints for the…
Multiply instructions for modular exponentiation
Granted: March 16, 2006
Application Number:
20060059221
A method and apparatus for increasing performance of a multiplication operation in a processor. The processor's instruction set includes multiply instructions that can be used to accelerate modular exponentiation. Prior to issuing a sequence of multiply instructions for the multiplication operation, a multiplier register in a multiply unit in the processor is loaded with the value of the multiplier. The multiply unit stores intermediate results of the multiplication operation in…
Multi-core debugger
Granted: March 16, 2006
Application Number:
20060059286
In a multi-core processor, a high-speed interrupt-signal interconnect allows more than one of the processors to be interrupted at substantially the same time. For example, a global signal interconnect is coupled to each of the multiple processors, each processor being configured to selectively provide an interrupt signal, or pulse thereon. Preferably, each of the processor cores is capable of pulsing the global signal interconnect during every clock cycle to minimize delay between a…
Local scratchpad and data caching system
Granted: March 16, 2006
Application Number:
20060059310
A RISC-type processor includes a main register file and a data cache. The data cache can be partitioned to include a local memory, the size of which can be dynamically changed on a cache block basis while the processor is executing instructions that use the main register file. The local memory can emulate as an additional register file to the processor and can reside at a virtual address. The local memory can be further partitioned for prefetching data from a non-cacheable address to be…
Direct access to low-latency memory
Granted: March 16, 2006
Application Number:
20060059314
A content aware application processing system is provided for allowing directed access to data stored in a non-cache memory thereby bypassing cache coherent memory. The processor includes a system interface to cache coherent memory and a low latency memory interface to a non-cache coherent memory. The system interface directs memory access for ordinary load/store instructions executed by the processor to the cache coherent memory. The low latency memory interface directs memory access…
