NETWORK SWITCHING WITH CO-RESIDENT DATA-PLANE AND NETWORK INTERFACE CONTROLLERS
Granted: January 24, 2019
Application Number:
20190028576
A system with co-resident data-plane and network interface controllers embodying a method for network switching of a data packet incoming from a network at a packet input processor portion of a network interface resource comprising the packet input processor, a packet output processor, and a network interface controller , implemented on a chip, to a target entity, is disclosed. Additionally, the system embodying a method for network switching of a data packet outgoing from an internal…
Method and Apparatus for Coordinated Multipoint Receiver Processing Acceleration and Latency Reduction
Granted: January 17, 2019
Application Number:
20190021013
Methods and apparatus for coordinated multipoint receiver processing acceleration and latency reduction. In an exemplary embodiment, an apparatus includes a receiver that receives symbols from a wireless transmission and stores the symbols in a memory. The receiver also outputs an indicator that indicates that storage of the symbols in the memory has begun. The apparatus also includes a controller that outputs control signaling in response to the indicator. The apparatus also includes a…
Methods And Apparatus For A Unified Baseband Architecture
Granted: December 6, 2018
Application Number:
20180352557
Methods and apparatus for a unified baseband architecture. In an exemplary embodiment, an apparatus includes a shared memory having a plurality of access ports and a scheduler that outputs scheduled jobs. Each scheduled job identifies data processing to be performed. The apparatus also includes a plurality of functional elements coupled to the plurality of access ports, respectively, to access the shared memory. Each functional element is operable to retrieve selected data from the…
PROGRAMMABLE HARDWARE SCHEDULER FOR DIGITAL PROCESSING SYSTEMS
Granted: December 6, 2018
Application Number:
20180349185
Method and system embodying the method for programmable scheduling encompassing: enqueueing at least one command into one of a plurality of queues having a plurality of entries; determining a category of the command at the head entry of each of the plurality of queues; processing each determined non-job category command by a non-job command arbitrator; and processing each determined job category command by a job arbitrator and assignor, is disclosed.
METHOD AND APPARATUS FOR SCHEDULING ARBITRATION AMONG A PLURALITY OF SERVICE REQUESTORS
Granted: December 6, 2018
Application Number:
20180349180
Method and system embodying the method for for scheduling arbitration among a plurality of service requestors encompassing: designating among the plurality of service requestors all the service requestors that have an active request; determining whether at least one of the designated service requestors has an un-served status indicator which is set; and when the determining is positive then: selecting one of the at least one designated service requestors in accordance with a…
RE-ORDERING BUFFER FOR A DIGITAL MULTI-PROCESSOR SYSTEM WITH CONFIGURABLE, SCALABLE, DISTRIBUTED JOB MANAGER
Granted: November 29, 2018
Application Number:
20180341602
A method utilizing a system encompassing a free pool buffer; a deadlock avoidance buffer; and a controller communicatively coupled to the free pool buffer and the deadlock avoidance buffer to reorder out-of-order responses to fetch requests into correct order by: receiving a fetch request on behalf of a consumer; allocating space first in the free pool buffer and when such space is not available then allocating space in a division associated with the consumer in the deadlock avoidance…
METHOD AND APPARATUS FOR LOAD BALANCING OF JOBS SCHEDULED FOR PROCESSING
Granted: November 22, 2018
Application Number:
20180336063
Method and system embodying the method for load balancing of scheduled jobs among a plurality of engines encompassing determining a number of cluster credits for each of a plurality of clusters that comprise at least one engine capable of processing a scheduled job; determining a number of engine credits for each of the plurality of engines comprising each of the at least one engine in accordance with a number of jobs assigned to each of the plurality of engines; evaluating the…
Methods and Apparatus for Adaptive Power Profiling in a Baseband Processing System
Granted: November 15, 2018
Application Number:
20180329472
Methods and apparatus for adaptive power profiling in a baseband processing system. In an exemplary embodiment, an apparatus includes one or more processing engines. Each processing engine performs at least one data processing function. The apparatus also includes an adaptive power profile (APP) and a job manager that receives job requests for data processing. The job manager allocates the data processing associated with the job requests to the processing engines based on the adaptive…
METHOD AND APPARATUS FOR JOB PRE-SCHEDULING BY DISTRIBUTED JOB MANAGER IN A DIGITAL MULTI-PROCESSOR SYSTEM
Granted: November 8, 2018
Application Number:
20180321983
A method and a system embodying the method for job pre-scheduling in a processing system comprising distributed job management, encompassing: determining a maximum amount of pre-schedulable jobs for each of a plurality of engines; setting for each of the plurality of engines a threshold less than or equal to the maximum amount; pre-scheduling by a scheduler an amount of jobs less than or equal to the threshold to at least one of a plurality of job managers; determining at the at least…
METHOD AND APPARATUS FOR PORT ACCESS MANAGEMENT AT A DISTRIBUTED JOB MANAGER IN A DIGITAL MULTI-PROCESSOR SYSTEM
Granted: November 8, 2018
Application Number:
20180321986
A method and a system for port access management at a distributed job manager, encompassing: initializing a port access process for each of one or more ports on a processing device; determining first whether a job is assigned to an active slot identified by an active_slot_id on the processing device, and when the determining is positive: determining second whether the job has been serviced by a port identified by the active_slot_id; and when either the first determining is negative or…
Methods and Apparatus for Control Bit Detection
Granted: November 1, 2018
Application Number:
20180316463
Methods and apparatus for control bit detection. In an exemplary embodiment, a method includes receiving an LLR sequence (l) that includes P control bits and calculating a sum of LLR squares parameter (L) associated with the LLR sequence. The method also includes generating a value (Vp) for each of the 2P combination of the control bits. Each Vp value is based on a parameter sequence and the LLR sequence. The method also includes determining a smallest value of Vp, and outputting a…
Methods and Apparatus for Calculating Transport Block (TB) Cyclic Redundancy Check (CRC) Values
Granted: October 4, 2018
Application Number:
20180287736
Methods and apparatus for calculating TB CRC values. In an exemplary embodiment, a method includes receiving code blocks (CBs) that form code block groups (CBGs), which form a transport block (TB), generating partial TB cyclic redundancy check (CRC) values from the CBGs, and processing the partial TB CRC values to determine a full TB CRC value. The method also includes comparing the full TB CRC value to a received TB CRC value to determine if the TB has been successfully received. An…
Method and Apparatus for Providing A Low Latency Transmission System Using Adaptive Buffering Estimation
Granted: August 23, 2018
Application Number:
20180241675
One aspect of the present invention discloses a network system capable of transmitting and processing audio video (“A/V”) data with enhanced quality of service (“QoS”). The network system includes a transmitter, a transmission channel, an adjustable decoder buffer, and a decoder. The transmitter contains an encoder able to encode A/V data in accordance with encoding bit rate recommendation from SQoS and packets loss notifications. The transmission channel, in one example,…
Methods and Apparatus for Frequency Offset Estimation
Granted: November 16, 2017
Application Number:
20170331664
Methods and apparatus for frequency offset estimation are disclosed. In an exemplary embodiment, a method includes determining a demodulation reference signal (DMRS) frequency offset estimate from DMRS symbols in a received signal, and determining a cyclic prefix (CP) frequency offset estimate from cyclic prefix values in the received signal. The method also includes combining the DMRS and CP frequency offset estimates to determine a final frequency offset estimate. In an exemplary…
METHOD AND APPARATUS FOR EFFICIENT AND FLEXIBLE DIRECT MEMORY ACCESS
Granted: November 16, 2017
Application Number:
20170329731
Method and system embodying the method for a direct memory access between a data storage and a data processing device via one or more direct memory access units, comprising transferring data between the data storage and a first direct memory access engine of a respective one or more direct memory access units and providing the data for a second direct memory access engine of the respective one or more direct memory access units; and transferring the data provided by the first direct…
METHOD AND APPARATUS FOR SHARED MULTI-PORT MEMORY ACCESS
Granted: October 19, 2017
Application Number:
20170301382
Method and system embodying the method for a general address transformation for an access to a shared memory comprising at least one tile and each tile comprising at least one memory bank, comprising selecting a mode of a general address transformation; providing a general address comprising a plurality of bits by at least one of a plurality of devices; and transforming the general address onto a transformed address according to the selected mode; wherein in a first selected mode the…
METHODS AND APPARATUS FOR PROVIDING AN FFT ENGINE USING A RECONFIGURABLE SINGLE DELAY FEEDBACK ARCHITECTURE
Granted: August 3, 2017
Application Number:
20170220523
Methods and apparatus for providing an FFT engine using a reconfigurable single delay feedback architecture. In one aspect, an apparatus includes a radix-2 (R2) single delay feedback (SDF) stage that generates a radix-2 output and a radix-3 (R3) SDF stage that generates a radix-3 output. The apparatus also includes one or more radix-2 squared (R2?2) SDF stages that generate a radix-4 output. The apparatus further includes a controller that configures a sequence of radix stages selected…
METHODS AND APPARATUS FOR A VECTOR MEMORY SUBSYSTEM FOR USE WITH A PROGRAMMABLE MIXED-RADIX DFT/IDFT PROCESSOR
Granted: July 6, 2017
Application Number:
20170192935
A vector memory subsystem for use with a programmable mix-radix vector processor (“PVP”) capable of calculating discrete Fourier transform (“DFT/IDFT”) values. In an exemplary embodiment, an apparatus includes a vector memory bank and a vector memory system (VMS) that generates input memory addresses that are used to store input data into the vector memory bank. The VMS also generates output memory addresses that are used to unload vector data from the memory banks. The input…
Methods and Apparatus for Twiddle Factor Generation for Use with a Programmable Mixed-Radix DFT/IDFT Processor
Granted: July 6, 2017
Application Number:
20170195281
Twiddle factor generation for use with a programmable mix-radix vector processor (“PVP”) capable of calculating discrete Fourier transform (“DFT/IDFT”) values. In an exemplary embodiment, an apparatus includes look-up table logic that receives twiddle control factors and outputs a selected twiddle factor scaler value (TFSV), a base vector generator that generates a base vector values based on the selected TFSV, and a twiddle column generator that generates a twiddle vector from…
Methods and Apparatus for Providing a Programmable Mixed-Radix DFT/IDFT Processor Using Vector Engines
Granted: July 6, 2017
Application Number:
20170192936
A programmable vector processor (“PVP”) capable of calculating discrete Fourier transform (“DFT/IDFT”) values is disclosed. In an exemplary embodiment, an apparatus includes a memory bank and a vector data path pipeline coupled to the memory bank. The apparatus also includes a configurable mixed radix engine coupled to the vector data path pipeline. The configurable mixed radix engine is configurable to perform a selected radix computation selected from a plurality of radix…
