Processing Of Finite Automata Based On Memory Hierarchy
Granted: October 15, 2015
Application Number:
20150293846
At least one processor may be operatively coupled to a plurality of memories and a node cache and configured to walk nodes of a per-pattern non-deterministic finite automaton (NFA). Nodes of the per-pattern NFA may be stored amongst one or more of the plurality of memories based on a node distribution determined as a function of hierarchical levels mapped to the plurality of memories and per-pattern NFA storage allocation settings configured for the hierarchical levels, optimizing run…
METHOD AND APPARATUS FOR LOW LATENCY EXCHANGE OF DATA BETWEEN A PROCESSOR AND COPROCESSOR
Granted: September 17, 2015
Application Number:
20150261535
According to at least one example embodiment, a method of processing a wide command includes storing wide command data in a first physical structure of a processor. Information associated with the wide command is determined based on the wide command data and/or a corresponding memory address range associated with the wide command. The information associated with the wide command determined includes a size of the wide command and is stored in a second physical structure of the processor.…
METHOD AND SYSTEM FOR ORDERING I/O ACCESS IN A MULTI-NODE ENVIRONMENT
Granted: September 10, 2015
Application Number:
20150254207
According to at least one example embodiment, a multi-chip system includes multiple chip devices configured to communicate to each other and share resources, such as I/O devices. According to at least one example embodiment, a method of synchronizing access to an input/output (I/O) device in the multi-chip system comprises initiating, by a first agent of the multi-chip system, a first operation for accessing the I/O device, the first operation is queued, prior to execution by the I/O…
INTER-CHIP INTERCONNECT PROTOCOL FOR A MULTI-CHIP SYSTEM
Granted: September 10, 2015
Application Number:
20150254183
A multi-chip system includes multiple chip devices configured to communicate to each other and share resources. According to at least one example embodiment, a method of providing memory coherence within the multi-chip system comprises maintaining, at a first chip device of the multi-chip system, state information indicative of one or more states of one or more copies, residing in one or more chip devices of the multi-chip system, of a data block. The data block is stored in a memory…
MULTI-CORE NETWORK PROCESSOR INTERCONNECT WITH MULTI-NODE CONNECTION
Granted: September 10, 2015
Application Number:
20150254182
According to at least one example embodiment, a method of data coherence is employed within a multi-chip system to enforce cache coherence between chip devices of the multi-node system. According at least one example embodiment, a message is received by a first chip device of the multiple chip devices from a second chip device of the multiple chip devices. The message triggers invalidation of one or more copies, if any, of a data block. The data block stored in a memory attached to, or…
METHOD AND SYSTEM FOR WORK SCHEDULING IN A MULTI-CHIP SYSTEM
Granted: September 10, 2015
Application Number:
20150254104
According to at least one example embodiment, a multi-chip system includes multiple chip devices configured to communicate to each other and share hardware resources. According to at least one example embodiment, a method of processing work item in the multi-chip system comprises designating, by a work source component associated with a chip device, referred to as the source chip device, of the multiple chip devices, a work item to a scheduler for scheduling. The scheduler then assigns…
Method and Apparatus for Memory Allocation in a Multi-Node System
Granted: September 10, 2015
Application Number:
20150253997
According to at least one example embodiment, a multi-chip system includes multiple chip devices configured to communicate to each other and share resources. According to at least one example embodiment, a method of memory allocation in the multi-chip system comprises managing, by each of one or more free-pool allocator (FPA) coprocessors in the multi-chip system, a corresponding list of pools of free-buffer pointers. Based on the one or more lists of free-buffer pointers managed by the…
PACKET OUTPUT PROCESSING
Granted: September 3, 2015
Application Number:
20150249603
A circuit operates to manage transmittal of packets in a network packet processor. The circuit includes a packet descriptor manager (PDM), a packet scheduling engine (PSE), and a packet engines and buffering module (PEB). The PDM generates a metapacket and a descriptor from a command signal, where the command signal identifies a packet to be transmitted by the circuit. The PSE determines an order in which to transmit the packet among a number of packets, where the PSE determines the…
PACKET SHAPING IN A NETWORK PROCESSOR
Granted: September 3, 2015
Application Number:
20150249620
A circuit operates to manage transmittal of packets in a network packet processor. The circuit includes a packet descriptor manager (PDM), a packet scheduling engine (PSE), and a packet engines and buffering module (PEB). The PDM generates a metapacket and a descriptor from a command signal, where the command signal identifies a packet to be transmitted by the circuit. The PSE compares a packet transmission rate associated with the packet against at least one of a peak rate and a…
PACKET SCHEDULING IN A NETWORK PROCESSOR
Granted: September 3, 2015
Application Number:
20150249604
A circuit operates to manage transmittal of packets in a network packet processor. The circuit includes a packet descriptor manager (PDM), a packet scheduling engine (PSE), and a packet engines and buffering module (PEB). The PDM generates a metapacket and a descriptor from a command signal, where the command signal identifies a packet to be transmitted by the circuit. The PSE models the packet through a model of the network topology, determining an order in which to transmit the packet…
SYSTEM ON CHIP LINK LAYER PROTOCOL
Granted: September 3, 2015
Application Number:
20150249602
A network processing system provides coherent communications between multiple system-on-chips (SOCs). Data messages between SOCs are assigned to virtual channels. An interconnect linking the SOCs divides the communications into discrete data blocks, each of which contains data segments from several virtual channels. The virtual channels can be implemented to control congestion and interference among classes of communications. During transmission, the interconnect distributes the data…
PARTITIONED ERROR CODE COMPUTATION
Granted: September 3, 2015
Application Number:
20150248323
A circuit provides parallel computation of error codes for simultaneously received words. The words received simultaneously may be portions of a common data message, or may be portions of distinct data messages. Accordingly, the circuit selectively accumulates the error codes based on their association with successive data words, outputting an accumulated error code when the last word of a data message has been received and the respective error code is calculated. Based on such…
Method And Apparatus For Power Gating Hardware Components In A Chip Device
Granted: September 3, 2015
Application Number:
20150248154
According to at least one example embodiment, a semiconductor device is configured to gate power supply to a hardware component through a transistor coupled to the hardware component. The transistor is operated by a controller in a manner to limit electric current dissipated to the hardware component during a transition period. The controller is configured to gradually turn on, or off, the hardware component during a transition period by controlling at least one input signal to the…
MULTIPLE ETHERNET PORTS AND PORT TYPES USING A SHARED DATA PATH
Granted: August 27, 2015
Application Number:
20150244649
In an embodiment an interface unit includes a transmit pipeline configured to transmit egress data, and a receive pipeline configured to receive ingress data. At least one of the transmit pipeline and the receive pipeline being may be configured to provide shared resources to a plurality of ports. The shared resources may include at least one of a data path resource and a control logic resource.
CDR VOTER WITH IMPROVED FREQUENCY OFFSET TOLERANCE
Granted: August 27, 2015
Application Number:
20150244549
An improved clock data recovery circuit is provided which provides lower bit error rates and faster locking times. In an embodiment, the circuit includes a voter having one or more voter inputs. The voter may generate up votes indicative of a recovered clock having a negative phase offset relative to a given voter input, or down votes indicative of the recovered clock having a positive phase offset. The circuit may include a comparator configured to output a phase adjustment signal and a…
Independent Ordering of Independent Threads
Granted: August 27, 2015
Application Number:
20150243357
In an embodiment, a method for managing access to memory includes receiving requests for access to a memory from one or more devices, each particular request associated with one of a plurality of virtual channels. A tag is assigned to each request received. Each tag assigned is added to a linked list associated with the corresponding virtual channel. Each request received with the assigned tag is transmitted to the memory. Responses to the requests are received from the memory, each…
Apparatus and Method for Software Enabled Access to Protected Hardware Resources
Granted: August 27, 2015
Application Number:
20150242655
A semiconductor includes a set of protected hardware resources, where at least one protected hardware resource stores a secure key. The semiconductor also includes a computation kernel and a memory to store a resource enablement module executed by the computation kernel. The resource enablement module selectively enables a protected hardware resource in response to a delivered key corresponding to the secure key.
METHOD AND AN APPARATUS FOR PRE-FETCHING AND PROCESSING WORK FOR PROCESOR CORES IN A NETWORK PROCESSOR
Granted: August 6, 2015
Application Number:
20150220360
A method and a system embodying the method for pre-fetching and processing work for processor cores in a network processor, comprising requesting pre-fetch work by a requestor; determining that the work may be pre-fetched for the requestor; searching for the work to pre-fetch; and pre-fetching the found work into one of one or more pre-fetch work-slots associated with the requestor is disclosed.
Method And Apparatus For Optimizing Finite Automata Processing
Granted: August 6, 2015
Application Number:
20150220845
A method, and corresponding apparatus and system are provided for optimizing matching at least one regular expression pattern in an input stream by walking at least one finite automaton in a speculative manner. The speculative manner may include iteratively walking at least two nodes of a given finite automaton, of the at least one finite automaton, in parallel, with a segment, at a current offset within a payload, of a packet in the input stream, based on positively matching the segment…
Finite Automata Processing Based on a Top of Stack (TOS) Memory
Granted: August 6, 2015
Application Number:
20150220454
A method, and corresponding apparatus and system are provided for optimizing matching of at least one regular expression pattern in an input stream by storing a context for walking a given node, of a plurality of nodes of a given finite automaton of at least one finite automaton, the store including a store determination, based on context state information associated with a first memory, for accessing the first memory and not a second memory or the first memory and the second memory.…
