SYSTEMS AND METHODS FOR SPECIFYING. MODELING, IMPLEMENTING AND VERIFYING IC DESIGN PROTOCOLS
Granted: June 4, 2015
Application Number:
20150154341
A new approach is proposed that contemplates systems and methods to support a hybrid verification framework (HVF) to design, verify, and implement design protocols for an integrated circuit (IC) chip such as a system-on-chip (SOC) and/or an application-specific integrated circuit (ASIC) chip. The framework creates a plurality of specifications in form of extended state transition tables for different phases of a design flow of the IC chip. The framework integrates and uses the extended…
VIRTUALIZED NETWORK INTERFACE FOR TCP REASSEMBLY BUFFER ALLOCATION
Granted: May 21, 2015
Application Number:
20150142977
A method and a system embodying the method for dynamically allocating context for Transmission Control Protocol (TCP) reassembly, comprising providing a fixed plurality of global common TCP contexts; reserving for each of one or more virtual network interface card(s) one or more TCP context(s) out of the fixed plurality of the global common TCP contexts; and allocating to a virtual network interface card from the one or more virtual network interface card(s) a TCP context from the…
Method and Apparatus to Represent a Processor Context with Fewer Bits
Granted: May 14, 2015
Application Number:
20150134931
According to at least one example embodiment, a method and corresponding processor device comprise maintaining a translation data structure mapping uncompressed process context identifiers to corresponding compressed identifiers, the uncompressed process context identifiers and the corresponding compressed identifiers being associated with address spaces or corresponding computer processes. The compressed identifiers are employed to probe, or access, one or more structures of the…
Method and Apparatus for Aligning Signals
Granted: April 9, 2015
Application Number:
20150100815
A method and corresponding apparatus for aligning a data signal with a corresponding clock signal include oversampling the data signal based on the corresponding clock signal and generating corresponding data samples. An indication of skew between the data signal and the corresponding clock signal is detected based on data samples. A variable delay line coupled to the data signal is then adjusted based on the indication of skew detected. According to at least one example implementation,…
Method And Apparatus For Supporting Wide Operations Using Atomic Sequences
Granted: April 9, 2015
Application Number:
20150100747
Implementations of wide atomic sequences are achieved by augmenting a load operation designed to initiate an atomic sequence and augmenting a conditional storing operation that typically terminates the atomic sequence. The augmented load operation is designed to further allocate a memory buffer besides initiating the atomic sequence. The conditional storing operation is augmented to check the allocated memory buffer for any data stored therein. If one or more data words are detected in…
Method And Apparatus For Conditional Storing Of Data Using A Compare-And-Swap Based Approach
Granted: April 9, 2015
Application Number:
20150100737
According to at least one example embodiment, a method and corresponding apparatus for conditionally storing data include initiating an atomic sequence by executing, by a core processor, an instruction/operation designed to initiate an atomic sequence. Executing the instruction designed to initiate the atomic sequence includes loading content associated with a memory location into a first cache memory, and maintaining an indication of the memory location and a copy of the corresponding…
Data Strobe Generation
Granted: April 9, 2015
Application Number:
20150098277
In an embodiment, a method of generating strobe signals includes generating a first strobe signal in a first mode by operating a multiplexer with a clock signal to select between a first input signal and a second input signal, the first input signal having a static first signal level and the second input signal corresponding to a control signal. In a second mode, the method includes generating a second strobe signal by operating the multiplexer with the clock signal to select between the…
Method and Apparatus for Amplifier Offset Calibration
Granted: April 2, 2015
Application Number:
20150092510
According to at least one example embodiment, a method and corresponding system for calibrating an amplifier offset include applying an input value to both input leads of an amplifier. The amplifier includes one or more digital-to-analog converters (DACs) used to calibrate an offset of the amplifier. A digital value, provided as input to the DAC, is updated over a number of iterations, by a control logic coupled to the amplifier, based on an output of the amplifier. A final value of the…
Auto-Blow Memory Repair
Granted: April 2, 2015
Application Number:
20150095732
In an example embodiment, a method may include collecting, at a controller within an integrated circuit, defect information indicative of defects identified during a built-in self-test (BIST) operation performed on plural memories embedded within the integrated circuit. Fuses within the integrated circuit may be blown based on the defect information collected automatically and without software intervention. The fuses blown may be used to inform a built-in self-repair (BISR) operation…
Method and Apparatus for Calibrating an Input Interface
Granted: April 2, 2015
Application Number:
20150092889
According to at least one example embodiment a two phase calibration approach is employed for calibrating an input/output interface having multiple single-ended receivers. During a first phase, amplifier offset calibration is applied to each of the multiple single-ended receivers. During a second phase, reference voltage calibration is applied to a single-ended receiver of the multiple single-ended receivers to determine a calibration reference voltage value. The calibration reference…
Dynamically Adjusting Supply Voltage Based On Monitored Chip Temperature
Granted: April 2, 2015
Application Number:
20150091638
In an embodiment, a method includes monitoring a temperature of a semiconductor chip and adjusting a supply voltage to the semiconductor chip based on the monitored temperature. The temperature may be monitored by a temperature sensor located on-chip or off-chip. Adjusting the supply voltage includes increasing the supply voltage as a function of the monitored temperature decreasing. The increase to the supply voltage occurs only if the monitored temperature is below a threshold…
Method and Apparatus for Reference Voltage Calibration in a Single-Ended Receiver
Granted: April 2, 2015
Application Number:
20150091631
According to at least one example embodiment, a method and corresponding system, or circuit, for calibrating a reference voltage of a single-ended receiver, include applying a clock signal and a reference voltage signal as inputs to the differential amplifier of the single-ended receiver. The differential amplifier provides an output signal, the output signal is processed, and an indication of a duty cycle associated with an output signal of the amplifier is evaluated. Based on the…
CLOCK MULTIPLEXING AND REPEATER NETWORK
Granted: April 2, 2015
Application Number:
20150091623
A system on chip (SOC) includes a clock generator to provide one or more on-chip reference clocks to a number of physical medium attachments (PMAs) across a common clock bus. The clock generator receives one or more external, off-chip clock lines, from which it generates the on-chip reference clocks. Each of the PMAs may operate data input/output (I/O) channels under a variety of different communications protocols, which can have common or distinct reference clock frequencies.…
Semiconductor with Virtualized Computation and Switch Resources
Granted: March 26, 2015
Application Number:
20150085868
A semiconductor substrate has a processor configurable to support execution of a hypervisor controlling a set of virtual machines and a physical switch configurable to establish virtual ports to the set of virtual machines.
Method and Apparatus for Managing Global Chip Power on a Multicore System on Chip
Granted: March 26, 2015
Application Number:
20150089251
According to at least one example embodiment, a method and corresponding apparatus for controlling power in a multi-core processor chip include: accumulating, at a controller within the multi-core processor chip, one or more power estimates associated with multiple core processors within the multi-core processor chip. A global power threshold is determined based on a cumulative power estimate, the cumulative power estimate being determined based at least in part on the one or more power…
Collapsed Address Translation With Multiple Page Sizes
Granted: March 26, 2015
Application Number:
20150089184
A computer system that supports virtualization may maintain multiple address spaces. Each guest operating system employs guest virtual addresses (GVAs), which are translated to guest physical addresses (GPAs). A hypervisor, which manages one or more guest operating systems, translates GPAs to root physical addresses (RPAs). A merged translation lookaside buffer (MTLB) caches translations between the multiple addressing domains, enabling faster address translation and memory access. The…
Translation Bypass In Multi-Stage Address Translation
Granted: March 26, 2015
Application Number:
20150089150
A computer system that supports virtualization may maintain multiple address spaces. Each guest operating system employs guest virtual addresses (GVAs), which are translated to guest physical addresses (GPAs). A hypervisor, which manages one or more guest operating systems, translates GPAs to root physical addresses (RPAs). A merged translation lookaside buffer (MTLB) caches translations between the multiple addressing domains, enabling faster address translation and memory access. The…
Maintenance Of Cache And Tags In A Translation Lookaside Buffer
Granted: March 26, 2015
Application Number:
20150089147
A computer system that supports virtualization may maintain multiple address spaces. Each guest operating system employs guest virtual addresses (GVAs), which are translated to guest physical addresses (GPAs). A hypervisor, which manages one or more guest operating systems, translates GPAs to root physical addresses (RPAs). A merged translation lookaside buffer (MTLB) caches translations between the multiple addressing domains, enabling faster address translation and memory access. The…
Merged TLB Structure For Multiple Sequential Address Translations
Granted: March 26, 2015
Application Number:
20150089116
A computer system that supports virtualization may maintain multiple address spaces. Each guest operating system employs guest virtual addresses (GVAs), which are translated to guest physical addresses (GPAs). A hypervisor, which manages one or more guest operating systems, translates GPAs to root physical addresses (RPAs). A merged translation lookaside buffer (MTLB) caches translations between the multiple addressing domains, enabling faster address translation and memory access. The…
Memory Interface With Integrated Tester
Granted: March 26, 2015
Application Number:
20150088437
In an embodiment, a memory interface includes integrated circuitry to verify the integrity of the memory interface. The circuitry propagates a test pattern through different paths of the memory interface, and checks the result against a reference value to determine whether the components of the paths are operating within an acceptable tolerance. The memory interface can also communicate with ATE to initiate such tests and return the results to the ATE.
