Method and Apparatus for Power Control
Granted: April 25, 2013
Application Number:
20130104130
Embodiments of the present invention relate to limiting maximum power dissipation occurred in a processor. Therefore, when an application that requires excessive amounts of power is being executed, the execution of the application may be prevented to reduce dissipated or consumed power.
Bit Error Rate Impact Reduction
Granted: April 25, 2013
Application Number:
20130104012
In an embodiment, a method includes receiving at a data interface a data stream having a plurality of logical communication channels. The data stream includes in succession a first data burst corresponding to one of the plurality of logical communication channels, a burst control word and a second data burst corresponding to the one or an other of the plurality of logical communication channels. The burst control word includes a first error check that protects the first data burst and…
SYSTEM AND METHOD TO PROVIDE NON-COHERENT ACCESS TO A COHERENT MEMORY SYSTEM
Granted: April 25, 2013
Application Number:
20130103909
In one embodiment, a system comprises a memory and a memory controller that provides a cache access path to the memory and a bypass-cache access path to the memory, receives requests to read graph data from the memory on the bypass-cache access path and receives requests to read non-graph data from the memory on the cache access path. A method comprises receiving a request at a memory controller to read graph data from a memory on a bypass-cache access path, receiving a request at the…
SYSTEM AND METHOD TO REDUCE MEMORY ACCESS LATENCIES USING SELECTIVE REPLICATION ACROSS MULTIPLE MEMORY PORTS
Granted: April 25, 2013
Application Number:
20130103904
In one embodiment, a system comprises multiple memory ports distributed into multiple subsets, each subset identified by a subset index and each memory port having an individual wait time. The system further comprises a first address hashing unit configured to receive a read request including a virtual memory address associated with a replication factor, and referring to graph data. The first address hashing unit translates the replication factor into a corresponding subset index based…
INPUT OUTPUT BRIDGING
Granted: April 25, 2013
Application Number:
20130103870
In one embodiment, a system comprises a memory, and a first bridge unit for processor access with the memory. The first bridge unit comprises a first arbitration unit that is coupled with an input-output bus, a memory free notification unit (“MFNU”), and the memory, and is configured to receive requests from the input-output bus and receive requests from the MFNU and choose among the requests to send to the memory on a first memory bus. The system further comprises a second bridge…
Polarity Detection
Granted: April 25, 2013
Application Number:
20130101076
In an embodiment, a method includes receiving at a data interface a data stream having a first polarity and searching the received data having the first polarity for a unique pattern of a synchronization word within a first quantity of the received data, the synchronization word marking a start of a metaframe having a metaframe length. The polarity of the data stream is reversed to a second polarity if the synchronization word is not found within the first quantity of the received data…
Word Boundary Lock
Granted: April 25, 2013
Application Number:
20130101069
In an embodiment, a method for determining a word boundary in an incoming data stream includes initializing an N bit register with initial content, receiving a number of consecutive N bit words of the incoming data stream and processing each of the number of consecutive N bit words. The processing includes performing operations per bit position of the register, including performing an XOR operation on a corresponding received data bit and a next received data bit, performing an AND…
MULTI-PROTOCOL SERDES PHY APPARATUS
Granted: April 25, 2013
Application Number:
20130101058
In one embodiment, a multiprotocol interface includes a physical layer transmitter unit configured to transmit data from synchronous media access control layer units and asynchronous media access control layer units. The multiprotocol interface also includes a physical layer receiver unit configured to receive data and to deliver the received data to the synchronous media access control layer units and the asynchronous media access control layer units. The physical layer transmitter unit…
PACKET PRIORITY IN A NETWORK PROCESSOR
Granted: April 25, 2013
Application Number:
20130100812
In a network processor, a “port-kind” identifier (ID) is assigned to each port. Parsing circuitry employs the port-kind ID to select the configuration information associate with a received packet. The port kind ID can also be stored at a data structure presented to software, along with a larger port number (indicating an interface and/or channel). Based on the port kind ID and extracted information about the packet, a backpressure ID is calculated for the packet. The backpressure ID…
Processor With Efficient Work Queuing
Granted: April 18, 2013
Application Number:
20130097608
Work submitted to a co-processor enters through one of multiple input queues, used to provide various quality of service levels. In-memory linked-lists store work to be performed by a network services processor in response to lack of processing resources in the network services processor. The work is moved back from the in-memory inked-lists to the network services processor in response to availability of processing resources in the network services processor.
PROCESSOR WITH DEDICATED VIRTUAL FUNCTIONS AND DYNAMIC ASSIGNMENT OF FUNCTIONAL RESOURCES
Granted: April 18, 2013
Application Number:
20130097598
In one embodiment, a processor comprises a plurality of hardware resources, each hardware resource having a clock cycle. The processor also comprises a plurality of work stores, each work store assigned into one of a plurality of virtual functions if a mode of the processor is set to a virtual function mode, and each work store assigned into one physical function if the mode of the processor is set to a physical function mode. The processor further comprises dispatch logic configured to…
QOS BASED DYNAMIC EXECUTION ENGINE SELECTION
Granted: April 18, 2013
Application Number:
20130097350
In one embodiment, a processor includes processing cores, and instruction stores storing instructions at least one instructions having a group number, each instruction store having a unique identifier. The processor also includes a group execution matrix having group execution masks and a store execution matrix having store execution masks. The processor further includes a core selection unit that, for each instruction, selects a store execution mask using the unique identifier as an…
Decision Tree Level Merging
Granted: April 4, 2013
Application Number:
20130085978
A packet classification system, methods, and corresponding apparatus are provided for enabling packet classification. A processor of a security appliance coupled to a network uses a classifier table having a plurality of rules, the plurality of rules having at least one field, to build a decision tree structure including a plurality of nodes, the plurality of nodes including a subset of the plurality of rules. By merging levels of decision trees, the methods may produce wider, shallower…
METHOD AND APPARATUS FOR MULTIPLE ACCESS OF PLURAL MEMORY BANKS
Granted: March 14, 2013
Application Number:
20130067173
A processor with on-chip memory including a plurality of physical memory banks is disclosed. The processor includes a method, and corresponding apparatus, of enabling multi-access to the plurality of physical memory banks The method comprises selecting a subset of multiple access requests to be executed in at least one clock cycle over at least one of a number of access ports connected to the plurality of physical memory banks, the selected subset of access requests addressed to…
Identifying Duplication in Decision Trees
Granted: March 7, 2013
Application Number:
20130060727
A packet classification system, methods, and corresponding apparatus are provided for enabling packet classification. A processor of a security appliance coupled to a network uses a classifier table having a plurality of rules, the plurality of rules having at least one field, to build a decision tree structure including a plurality of nodes, the plurality of nodes including a subset of the plurality of rules. By identifying duplication in decision trees, the methods may produce wider,…
LOOKUP FRONT END PACKET INPUT PROCESSOR
Granted: March 7, 2013
Application Number:
20130058332
A packet processor provides for rule matching of packets in a network architecture. The packet processor includes a lookup cluster complex having a number of lookup engines and respective on-chip memory units. The on-chip memory stores rules for matching against packet data. A lookup front-end receives lookup requests from a host, and processes these lookup requests to generate key requests for forwarding to the lookup engines. As a result of the rule matching, the lookup engine returns…
Packet Classification
Granted: February 14, 2013
Application Number:
20130039366
A packet classification system, methods, and corresponding apparatus are provided for enabling packet classification. A processor of a security appliance coupled to a network uses a classifier table having a plurality of rules, the plurality of rules having at least one field, to build a decision tree structure including a plurality of nodes, the plurality of nodes including a subset of the plurality of rules. The methods may produce wider, shallower trees that result in shorter search…
WORK MIGRATION IN A PROCESSOR
Granted: February 7, 2013
Application Number:
20130036151
A packet processor provides for rule matching of packets in a network architecture. The packet processor includes a lookup cluster complex having a number of lookup engines and respective on-chip memory units. The on-chip memory stores rules for matching against packet data. Each of the lookup engines receives a key request associated with a packet and determines a subset of the rules to match against the packet data. A work product may be migrated between lookup engines to complete the…
System and Method for Storing Lookup Request Rules in Multiple Memories
Granted: February 7, 2013
Application Number:
20130036083
In one embodiment, a system includes a data navigation unit configured to navigate through a data structure stored in a first memory to a first representation of at least one rule. The system further includes at least one rule processing unit configured to a) receive the at least one rule based on the first representation of the at least one rule from a second memory to one of the rule processing unit, and b) processing a key using the at least one rule.
LOOKUP CLUSTER COMPLEX
Granted: February 7, 2013
Application Number:
20130034106
A packet processor provides for rule matching of packets in a network architecture. The packet processor includes a lookup cluster complex having a number of lookup engines and respective on-chip memory units. The on-chip memory stores rules for matching against packet data. Each of the lookup engines receives a key request associated with a packet and determines a subset of the rules to match against the packet data. As a result of the rule matching, the lookup engine returns a response…
