OXIDE FORMATION IN A PLASMA PROCESS
Granted: March 21, 2019
Application Number:
20190088669
A memory transistor includes a gate electrode and a blocking structure disposed beneath the gate electrode, where the blocking structure is formed by plasma oxidation. The memory transistor includes a multi-layer charge storage layer disposed beneath the blocking structure, wherein the multi-layer charge storage layer includes a trap dense charge storage layer over a substantially trap free charge storage layer, where a thickness of the trap dense charge storage layer is reduced by the…
EMBEDDED SONOS WITH TRIPLE GATE OXIDE AND MANUFACTURING METHOD OF THE SAME
Granted: March 21, 2019
Application Number:
20190088487
A method to integrate silicon-oxide-nitride-oxide-silicon (SONOS) transistors into a complementary metal-oxide-semiconductor (CMOS) flow including a triple gate oxide structure. The memory device may include a non-volatile memory (NVM) transistor that has a charge-trapping layer and a blocking dielectric, a first field-effect transistor (FET) including a first gate oxide of a first thickness, a second FET including a second gate oxide of a second thickness, a third FET including a third…
2T1C Ferro-electric Random Access Memory Cell
Granted: March 21, 2019
Application Number:
20190088320
A memory device and method of operating the same are disclosed. Generally, the device includes an array of Ferro-electric Random Access Memory cells. Each cell includes a first transistor coupled between a bit-line and a storage node (SN) and controlled by a first wordline (WL1), a second transistor coupled between a reference line and the SN and controlled by a second wordline (WL2), and a ferro-capacitor coupled between the SN and a plateline. The device further includes a…
LOW STANDBY POWER WITH FAST TURN ON METHOD FOR NON-VOLATILE MEMORY DEVICES
Granted: March 14, 2019
Application Number:
20190080732
A method for driving a non-volatile memory system is disclosed. A standby detection circuit detects whether the nonvolatile memory system is in a standby condition. In response to determining that the non-volatile memory system is in a standby condition, a bias control circuit reduces bias currents provided to drivers of the non-volatile memory system in a standby mode. The non-volatile memory system is operated in the standby mode after the bias currents have been reduced, where an…
SUPPRESSING NOISE IN TOUCH PANELS USING A SHIELD LAYER
Granted: March 14, 2019
Application Number:
20190079634
A method, apparatus, and system measure, at a first channel of a processing device, a first signal indicative of a touch object proximate to an electrode layer. The first signal includes a touch data component and a first noise component generated by a noise source. The method, apparatus, and system measure, at a second channel of the processing device, a second signal including a second noise component generated by the noise source. The second channel is coupled to a shield layer…
METHOD OF REDUCING CHARGE LOSS IN NON-VOLATILE MEMORIES
Granted: March 7, 2019
Application Number:
20190074286
An example embodiment comprises a method for fabrication of a non-volatile memory (NVM) device. An isolation structure is formed in a substrate between first and second locations for first and second NVM cells. A common charge trapping layer is formed as a continuous structure over the substrate, where a first portion of the charge trapping layer is disposed directly over the isolation structure and second portions of the charge trapping layer are disposed directly over the first and…
NANO-POWER CAPACITANCE-TO-DIGITAL CONVERTER
Granted: March 7, 2019
Application Number:
20190072597
An asynchronous capacitance-to-digital converter (CDC) is described that allows for very low-power operation when during inactive periods (when no conductive object is in contact or proximity to the sensing electrodes). Asynchronous operation of the CDC provides for capacitance-to-digital conversion without the use of system resources and more power intensive circuit elements.
METHOD OF INTEGRATING A CHARGE-TRAPPING GATE STACK INTO A CMOS FLOW
Granted: February 28, 2019
Application Number:
20190067313
A method of fabricating a memory device is described. Generally, the method includes: forming on a surface of a substrate a dielectric stack including a tunneling dielectric and a charge-trapping layer overlying the tunneling dielectric; forming a cap layer overlying the dielectric stack, wherein the cap layer comprises a multi-layer cap layer including at least a first cap layer overlying the charge-trapping layer, and a second cap layer overlying the first cap layer; patterning the cap…
SMART SYRINGE
Granted: February 28, 2019
Application Number:
20190060577
A smart syringe is described that is capable of measuring a position of a plunger within the barrel of the smart syringe and of communicating the status of a liquid pharmaceutical within the smart syringe to a patient database.
Inter-Layer Insulator for Electronic Devices and Apparatus for Forming Same
Granted: February 7, 2019
Application Number:
20190043751
A semiconducting device utilizing air-gaps for inter-layer insulation and methods of producing the device are described. The device may be produced by forming a sacrificial layer between two structures. A porous membrane layer is then formed over the sacrificial layer. The membrane layer is porous to an etch product, which allows for the subsequent etching of the sacrificial layer leaving an air gap between the device structures and the membrane intact. The device may also include a cap…
GENERATING AND ANALYZING NETWORK PROFILE DATA
Granted: January 31, 2019
Application Number:
20190036965
A device may generate network profile data indicating a set of network parameters detected by the device. The device may encrypt the network profile data and may transmit the encrypted network profile data to a network device, such as a router, or a server. The router or server may analyze the encrypted network profile data to determine if the device is secure. The router of server may perform one or more security measures if the device is not secure.
METHODS, CIRCUITS, DEVICES, AND SYSTEMS FOR SENSING AN NVM CELL
Granted: January 31, 2019
Application Number:
20190035477
Disclosed is a non-volatile memory (NVM) device including an array of NVM cells segmented into at least a first sector and a second sector and at least one sensing circuit to sense a state of a target NVM cell in the first sector using a reference current of the second sector received from at least a dynamic reference cell.
SYSTEM PROVIDING AUTOMATIC SOURCE CODE GENERATION FOR PERSONALIZATION AND PARAMETERIZATION OF USER MODULES
Granted: January 31, 2019
Application Number:
20190034175
A method and system of automatically generating source code for configuring a programmable microcontroller. The method involves displaying virtual blocks in a computerized design system where the virtual blocks correspond to programmable circuit blocks in a microcontroller chip. The user selects a user module that defines a particular function to be performed on the microcontroller. The user assigns the virtual blocks to the user module. The design system then automatically generates…
Method of Forming High-Voltage Transistor with Thin Gate Poly
Granted: January 24, 2019
Application Number:
20190027487
A semiconductor device and method of fabricating the same are disclosed. The method includes depositing a polysilicon gate layer over a gate dielectric formed over a surface of a substrate in a peripheral region, forming a dielectric layer over the polysilicon gate layer and depositing a height-enhancing (HE) film over the dielectric layer. The HE film, the dielectric layer, the polysilicon gate layer and the gate dielectric are then patterned for a high-voltage Field Effect Transistor…
EMBEDDED NON-VOLATILE MEMORY DEVICE AND FABRICATION METHOD OF THE SAME
Granted: January 24, 2019
Application Number:
20190027484
Systems and methods of forming such include method, forming a memory gate (MG) stack in a first region, forming a sacrificial polysilicon gate on a high-k dielectric in a second region, wherein the first and second regions are disposed in a single substrate. Then a select gate (SG) may be formed adjacent to the MG stack in the first region of the semiconductor substrate. The sacrificial polysilicon gate may be replaced with a metal gate to form a logic field effect transistor (FET) in…
MICROCONTROLLER PROGRAMMABLE SYSTEM ON A CHIP
Granted: January 10, 2019
Application Number:
20190012287
Embodiments of the present invention are directed to a microcontroller device having a microprocessor, programmable memory components, and programmable analog and digital blocks. The programmable analog and digital blocks are configurable based on programming information stored in the memory components. Programmable interconnect logic, also programmable from the memory components, is used to couple the programmable analog and digital blocks as needed. The advanced microcontroller design…
REDUCING SLEEP CURRENT IN A CAPACITANCE SENSING SYSTEM
Granted: January 10, 2019
Application Number:
20190012010
An apparatus and method of measuring a collective capacitance on a group of capacitive sense elements from at least one of rows or columns of a capacitance sense array when in a first mode, and individually measuring capacitances on each of the rows and columns when in a second mode.
Multiphase Fingerprint Sensor Layout and Construction
Granted: January 3, 2019
Application Number:
20190005293
A capacitive fingerprint sensor includes a set of capacitive sensor electrodes in a sensing area. The set of capacitive sensor electrodes includes a set of transmit (Tx) sensor electrodes, a set of receive (Rx) sensor electrodes, and a set of compensation electrodes. The fingerprint sensor also includes a multiphase capacitance sensor that is configured to perform a sensing scan of the capacitive sensor electrodes by applying a first Tx signal to a first subset of the Tx sensor…
OPTICAL MONITORING OF TARGET CHARACTERISTICS
Granted: December 20, 2018
Application Number:
20180364150
An optical monitor includes a target disposed within the optical monitor and exposed to ambient air, wherein exposure to the ambient air produces a change in an optical property of the target. The optical monitor may also include a light emitter to illuminate the target and an optical detector to generate a signal based on light reflected from or transmitted through the target. A processing device may activate the light emitter and receive the signal from the optical detector.
SENSOR-COMPATIBLE OVERLAY
Granted: December 20, 2018
Application Number:
20180365476
A fingerprint sensor-compatible overlay material which uses anisotropic conductive material to enable accurate imaging of a fingerprint through an overlay is disclosed. The anisotropic conductive material has increased conductivity in a direction orthogonal to the fingerprint sensor, increasing the capacitive coupling of the fingerprint to the sensor surface, allowing the fingerprint sensor to accurately image the fingerprint through the overlay. Methods for forming a fingerprint…
