OXIDE-NITRIDE-OXIDE STACK HAVING MULTIPLE OXYNITRIDE LAYERS
Granted: December 20, 2018
Application Number:
20180366564
An embodiment of a semiconductor memory device including a multi-layer charge storing layer and methods of forming the same are described. Generally, the device includes a channel formed from a semiconducting material overlying a surface on a substrate connecting a source and a drain of the memory device; a tunnel oxide layer overlying the channel; and a multi-layer charge storing layer including an oxygen-rich, first oxynitride layer on the tunnel oxide layer in which a stoichiometric…
OXIDE-NITRIDE-OXIDE STACK HAVING MULTIPLE OXYNITRIDE LAYERS
Granted: December 20, 2018
Application Number:
20180366563
An embodiment of a semiconductor memory device including a multi-layer charge storing layer and methods of forming the same are described. Generally, the device includes a channel formed from a semiconducting material overlying a surface on a substrate connecting a source and a drain of the memory device; a tunnel oxide layer overlying the channel; and a multi-layer charge storing layer including an oxygen-rich, first oxynitride layer on the tunnel oxide layer in which a stoichiometric…
Memory First Process Flow and Device
Granted: December 20, 2018
Application Number:
20180366551
A semiconductor device and method of making the same are disclosed. The semiconductor device includes a memory gate on a charge storage structure formed on a substrate, a select gate on a gate dielectric on the substrate proximal to the memory gate, and a dielectric structure between the memory gate and the select gate, and adjacent to sidewalls of the memory gate and the select gate, wherein the memory gate and the select gate are separated by a thickness of the dielectric structure.…
NAND MEMORY CELL STRING HAVING A STACKED SELECT GATE STRUCTURE AND PROCESS FOR FOR FORMING SAME
Granted: December 20, 2018
Application Number:
20180366473
A memory string is disclosed including a plurality of core cells serially connected between a source select gate and a drain select gate along a channel. Each core cell includes a wordline separated from the channel by a stack of layers including a charge trapping layer. At least one of the source and drain select gates is a stacked select gate with a plurality of components, including a first component adjacent to the plurality of core cells and a second component separated from the…
SPLIT-GATE SEMICONDUCTOR DEVICE WITH L-SHAPED GATE
Granted: December 13, 2018
Application Number:
20180358367
A semiconductor device having a substrate, a dielectric layer over the substrate, a first gate conductor, an inter-gate dielectric structure and a second gate conductor is disclosed. A gate dielectric structure is disposed between the first gate conductor and the dielectric layer, and may include two or more dielectric films disposed in an alternating manner. The inter-gate dielectric structure may be disposed between the first gate conductor and the second gate conductor, and may…
ASYMMETRIC PASS FIELD-EFFECT TRANSISTOR FOR NONVOLATILE MEMORY
Granted: December 13, 2018
Application Number:
20180358097
A method of performing an operation on a non-volatile memory (NVM) cell of a memory device is disclosed. The pass transistor of the NVM cell is an asymmetric transistor including a source with a halo implant. The source of the pass transistor is coupled to a common source line (CSL) that is shared among NVM cells of a sector of NVM cells. The operation may be performed by applying a first signal to a word line (WLS) coupled to a gate of a memory transistor of the NVM cell and applying a…
BLOCK MAPPING SYSTEMS AND METHODS FOR STORAGE DEVICE
Granted: December 6, 2018
Application Number:
20180349268
An overlaid erase block (EB) mapping scheme for a flash memory provides efficient wear-leveling and reduces mount operation latency. The overlaid EB mapping scheme maps a first type of EB onto one of a plurality of physical erase blocks, in a corresponding portion of the flash memory. The first type of EB includes a plurality of pointers. The overlaid EB mapping scheme also maps each of second and third types of EBs onto one of the physical EBs that is not mapped to the first type of EB.…
Radical Oxidation Process For Fabricating A Nonvolatile Charge Trap Memory Device
Granted: December 6, 2018
Application Number:
20180351004
A method for fabricating a nonvolatile charge trap memory device is described. The method includes subjecting a substrate to a first oxidation process to form a tunnel oxide layer overlying a polysilicon channel, and forming over the tunnel oxide layer a multi-layer charge storing layer comprising an oxygen-rich, first layer comprising a nitride, and an oxygen-lean, second layer comprising a nitride on the first layer. The substrate is then subjected to a second oxidation process to…
SONOS ONO STACK SCALING
Granted: December 6, 2018
Application Number:
20180351003
A method of scaling a nonvolatile trapped-charge memory device and the device made thereby is provided. In an embodiment, the method includes forming a channel region including polysilicon electrically connecting a source region and a drain region in a substrate. A tunneling layer is formed on the substrate over the channel region by oxidizing the substrate to form an oxide film and nitridizing the oxide film. A multi-layer charge trapping layer including an oxygen-rich first layer and…
SYSTEM AND METHODS FOR AUDIO PATTERN RECOGNITION
Granted: December 6, 2018
Application Number:
20180350357
An example apparatus provides an input signal based on sound waves received by one or more microphones. The input signal includes a voice command component and one or more interference components. The apparatus receives audio data over one or more computer networks and the audio data corresponds to the one or more interference components. The apparatus uses the audio data to remove a portion of the one or more interference components from the input signal to generate an output signal,…
BOOTING AN APPLICATION FROM MULTIPLE MEMORIES
Granted: December 6, 2018
Application Number:
20180349262
A method includes using a memory address map, locating a first portion of an application in a first memory and loading a second portion of the application from a second memory. The method includes executing in place from the first memory the first portion of the application, during a first period, and by completion of the loading of the second portion of the application from the second memory. The method further includes executing the second portion of the application during a second…
ESTIMATING ANGLE MEASUREMENTS FOR SOURCE TRACKING USING A PHASED ARRAY SYSTEM
Granted: December 6, 2018
Application Number:
20180348357
A method includes using a receiver of a first device, receiving from a second device, radio frequency (RF) signals. The method also includes using a processor of the first device, determining and storing, based on the RF signals, a set of angle-estimation values of an angle between a plurality of antenna elements of one of the first device and the second device and an antenna element of the other of the first device and the second device, a set of confidence measurements, and at least…
DISTRIBUTED AND SYNCHRONIZED CONTROL SYSTEM FOR ENVIRONMENTAL SIGNALS IN MULTIMEDIA PLAYBACK
Granted: November 22, 2018
Application Number:
20180336929
A method includes providing a media dataset including media content data and environmental effects metadata defining a set of environmental events each corresponding to a media timestamp of a plurality of media timestamps. The method further includes, for each environmental event in the set of environmental events, identifying a protocol timestamp for a communication protocol, where the protocol timestamp corresponds to the media timestamp of the environmental event, and generating a…
USB Power Control Analog Subsystem Architecture
Granted: November 22, 2018
Application Number:
20180335818
A device and method that include a power control analog subsystem of a universal serial bus (USB) compatible power supply device is disclosed. The power control analog subsystem includes a programmable reference generator to generate first reference voltages. The power control analog subsystem also includes multiplexers, where each of a plurality of multiplexers are coupled to a first terminal and a second terminal of a producer field-effect transistor (FET) to receive a first voltage…
Programmable Shunt Regulator
Granted: November 22, 2018
Application Number:
20180335792
A device and method that includes a shunt regulator of a universal serial bus (USB) compatible power supply device is disclosed. The shunt regulator includes an amplifier with an output, a first input, and a second input. The shunt regulator also includes a current digital-to-analog converter (DAC) that is coupled to the first input of the amplifier and a voltage bus node. The current DAC adjusts a sink or a source current delivered at the first input of the amplifier to regulate a…
CURRENT SENSING IN A USB POWER CONTROL ANALOG SUBSYSTEM
Granted: November 22, 2018
Application Number:
20180335454
A device includes a power control analog subsystem of a universal serial bus-power delivery (USB-PD) compatible power supply device. The power control analog subsystem includes a programmable current sensing circuit and a current sense resistor coupled to the power control analog subsystem. The power control analog subsystem is configured to concurrently compare a current flow through the current sense resistor with at least three different reference values, e.g., compare a sensed…
Charge Trapping Split Gate Device and Method of Fabricating Same
Granted: November 8, 2018
Application Number:
20180323314
A split gate device that includes a memory gate and a select gate disposed side by side, a dielectric structure having a first portion disposed between the memory gate and a substrate and a second portion disposed along an inner sidewall of the select gate to separate the select gate from the memory gate, and a spacer formed over the select gate along an inner sidewall of the memory gate. Other embodiments of embedded split gate devices including high voltage and low voltage transistors…
VERTICAL DIVISION OF THREE-DIMENSIONAL MEMORY DEVICE
Granted: November 8, 2018
Application Number:
20180323208
A method of forming a vertical non-volatile (NV) memory device such as 3-D NAND flash memory includes forming a vertical NV memory cell string within an opening disposed in a stack of alternating layers of a first layer and a second layer over a substrate, and dividing the vertical NV memory cell string into two halves with a first vertical deep trench and an isolation dielectric pillar formed in the first vertical deep trench, such that memory bit density of the divided vertical NV…
Combined Analog Architecture and Functionality in a Mixed-Signal Array
Granted: October 11, 2018
Application Number:
20180292454
A programmable device comprises a plurality of programmable blocks, a debug interface coupled with the plurality of programmable blocks, a debug interface coupled with the plurality of programmable blocks, and a power manger coupled with the plurality of programmable blocks. The power manager is configured to supply power to a subset of the plurality of programmable blocks during debugging of the subset while maintaining a different subset of the plurality of programmable blocks in a…
DEVELOPMENT, PROGRAMMING, AND DEBUGGING ENVIRONMENT
Granted: October 11, 2018
Application Number:
20180293332
A method includes providing a design interface to design a device schematic for a programmable device and receiving a placement of graphical objects in the device schematic, wherein the graphical objects represent components that are both internal and external to the programmable device being configured. The method further includes assigning the graphical objects into one of an internal domain and an external domain and displaying, by the processing device, the graphical objects from…
