SYSTEMS AND METHODS FOR DOWNLOADING CODE AND DATA INTO A SECURE NON-VOLATILE MEMORY
Granted: October 5, 2017
Application Number:
20170287366
An example secure embedded device includes a secure non-volatile memory coupled to a processor. The processor provides a scramble or cipher key and uses a scramble algorithm or a cipher algorithm to scramble or cipher information received from an external device into transformed information. The processor writes a least a portion of the transformed information to a plurality of memory locations of the secure non-volatile memory. The plurality of memory locations is based on the scramble…
INTEGRATION OF A MEMORY TRANSISTOR INTO HIGH-K, METAL GATE CMOS PROCESS FLOW
Granted: September 28, 2017
Application Number:
20170278853
Memory cells including embedded SONOS based non-volatile memory (NVM) and MOS transistors and methods of forming the same are described. Generally, the method includes: forming a gate stack of a NVM transistor in a NVM region of a substrate including the NVM region and a plurality of MOS regions; and depositing a high-k dielectric material over the gate stack of the NVM transistor and the plurality of MOS regions to concurrently form a blocking dielectric comprising the high-k dielectric…
SYSTEMS, METHODS, AND APPARATUS FOR MEMORY CELLS WITH COMMON SOURCE LINES
Granted: September 28, 2017
Application Number:
20170278573
Systems, methods, and apparatus are disclosed for implementing memory cells having common source lines. The methods may include receiving a first voltage at a first transistor. The first transistor may be coupled to a second transistor and included in a first memory cell. The methods include receiving a second voltage at a third transistor. The third transistor may be coupled to a fourth transistor and included in a second memory cell. The first and second memory cells may be coupled to…
LOW-POWER TOUCH BUTTON SENSING SYSTEM
Granted: September 28, 2017
Application Number:
20170277241
A method for operating a sensing system includes receiving, from a processing device, control information for configuring a capacitance sensing circuit, configuring the capacitance sensing circuit with the control information in response to receiving the control information, and controlling power consumption of the processing device based on the control information and based on a capacitance measured by the capacitance sensing circuit.
Single Layer Sensor Pattern
Granted: September 14, 2017
Application Number:
20170262097
A capacitive sensor array comprises large sensor electrodes and small sensor electrodes formed from a single layer of conductive material. Each sensor electrode of a first set of small sensor electrodes is electrically connected to a first pad. A first axis crosses two or more of the sensor electrodes of the first set of small sensor electrodes, and each small sensor electrode of the first set of small sensor electrodes is located on an opposite lateral side of one of the large sensor…
TRANSCEIVER FOR COMMUNICATION AND METHOD FOR CONTROLLING COMMUNICATION
Granted: September 14, 2017
Application Number:
20170264376
An example embodiment provides a transceiver for communication includes a timing determiner that detects a fall from high level to low level of a bus signal generated by pulse width modulation of a clock signal and input from a communication bus; a transmission data signal delay adjuster that determines a second timing having a predetermined time difference from a first timing, the bus signal rising from the low level to the high level at the first timing; an encoder that extends a low…
Embedded SONOS Based Memory Cells
Granted: September 14, 2017
Application Number:
20170263622
Memory devices and methods for forming the same are disclosed. In one embodiment, the device includes a non-volatile memory (NVM) transistor formed in a first region of a substrate, the NVM transistor comprising a channel and a gate stack on the substrate overlying the channel. The gate stack includes a dielectric layer on the substrate, a charge-trapping layer on the dielectric layer, an oxide layer overlying the charge-trapping layer, a first gate overlying the oxide layer, and a first…
MULTI-LAYER INTER-GATE DIELECTRIC STRUCTURE AND METHOD OF MANUFACTURING THEREOF
Granted: September 14, 2017
Application Number:
20170263459
A semiconductor device having a first gate stack on a substrate is disclosed. The first gate stack may include a first gate conductor over a first gate dielectric structure. A dielectric structure can be formed over the first gate stack and the substrate. The dielectric structure layer can include four or more layers of two or more dielectric films disposed in an alternating manner. The dielectric structure can be selectively etched to form an inter-gate dielectric structure. A second…
10-Transistor Non-Volatile Static Random-Access Memory Using A Single Non-Volatile Memory Element And Method Of Operation Thereof
Granted: September 14, 2017
Application Number:
20170263309
A memory including an array of nvRAM cells and method of operating the same are provided. Each nvRAM cell includes a volatile charge storage circuit, and a non-volatile charge storage circuit including a solitary non-volatile memory (NVM) device, a first transistor coupled to the NVM device through which data is coupled to the volatile charge storage circuit, a second transistor coupled to the NVM device through which a compliment of the data is coupled to the volatile charge storage…
Fingerprint Sensor-Compatible Overlay Material
Granted: September 14, 2017
Application Number:
20170262685
A fingerprint sensor-compatible overlay material which uses anisotropic conductive material to enable accurate imaging of a fingerprint through an overlay is disclosed. The anisotropic conductive material has increased conductivity in a direction orthogonal to the fingerprint sensor, increasing the capacitive coupling of the fingerprint to the sensor surface, allowing the fingerprint sensor to accurately image the fingerprint through the overlay. Methods for forming a fingerprint…
Sensor Array with Edge Pattern
Granted: September 14, 2017
Application Number:
20170262094
A capacitive sensor array may include a first set of sensor electrodes and a second set of sensor electrodes. Each of the second set of sensor electrodes may intersect each of the first set of sensor electrodes to form a plurality of unit cells each corresponding to a pair of sensor electrodes including one of the first set of sensor electrodes and one of the second set of sensor electrodes. Each point within each of the plurality of unit cells may nearer to a gap between the pair of…
TYPE-C CONNECTOR SUBSYSTEM
Granted: September 14, 2017
Application Number:
20170262035
A Universal Serial Bus (USB) Type-C connector subsystem is described herein. An integrated circuit (IC) chip device includes a Universal Serial Bus (USB) Type-C subsystem. The USB Type-C subsystem is to operate an Ra termination circuit that consumes no more than a first predetermined amount of current after the Ra termination circuit is applied to a Vconn line of the Type-C subsystem, or to operate a standby reference circuit in a low power mode of the device to perform detection on a…
Capacitive Sensing Button On Chip
Granted: September 7, 2017
Application Number:
20170255297
A method and apparatus include a plurality of sensor elements arranged within an integrated circuit package and a controller arranged within the integrated circuit package and coupled to the plurality of sensor elements. The controller is configured to apply a transmit signal to a first sensor element of the plurality of sensor elements and receive a receive signal from a second sensor element of the plurality of sensor elements. The receive signal represents a mutual capacitance of the…
Non-Volatile Memory With Silicided Bit Line Contacts
Granted: August 31, 2017
Application Number:
20170250192
An approach to use silicided bit line contacts that do not short to the underlying substrate in memory devices. The approach provides for silicide formation in the bit line contact area, using a process that benefits from being self-aligned to the oxide-nitride-oxide (ONO) nitride edges. A further benefit of the approach is that the bit line contact implant and rapid temperature anneal process can be eliminated. This approach is applicable to embedded flash, integrating high density…
SYSTEMS, METHODS, AND DEVICES FOR PARALLEL READ AND WRITE OPERATIONS
Granted: August 31, 2017
Application Number:
20170249978
Disclosed herein are systems, methods, and devices for parallel read and write operations. Devices may include a first transmission device coupled to a local bit line and a global bit line associated with a memory unit of a memory array. The first transmission device may be configured to selectively couple the global bit line to the local bit line. The devices may further include a first device coupled to the local bit line and a sense amplifier. The first device may be configured to…
Manufacturing of FET Devices Having Lightly Doped Drain and Source Regions
Granted: August 3, 2017
Application Number:
20170221768
Embodiments described herein generally relate to methods of manufacturing n-type lightly doped drains and p-type lightly doped drains. In one method, photoresist mask is used to etch a transistor, and the mask is left in place (i.e., reused) to protect other devices and poly while a high energy implantation is performed in alignment with the photoresist mask, such that the implantation is adjacent to the etched transistor. One example of a high energy implantation is forming lightly…
Quasi-differential Mutual Capacitance Measurement
Granted: July 20, 2017
Application Number:
20170205453
A circuit, system, and method for converting mutual capacitance to a digital value is described. Charge packets are transferred from a mutual capacitance to a pair of integration capacitors during alternate charge and discharge cycles. The time required to bring the discharged integration capacitor to the same potential as the charged integration capacitor with a current source is measured as a single-slope analog-to-digital converter (ADC). The output of the ADC is representative of the…
Configurable Capacitor Arrays and Switched Capacitor Circuits
Granted: July 13, 2017
Application Number:
20170201266
Methods and apparatus include and amplifier circuit and a first capacitor branch including a first plurality of capacitors. The first capacitor branch couples to an input signal and to an input of the amplifier circuit. A second capacitor branch includes a second plurality of capacitors. The second capacitor branch couples to the input of the amplifier circuit and to an output of the amplifier circuit.
Split Gate Charge Trapping Memory Cells Having Different Select Gate and Memory Gate Heights
Granted: July 6, 2017
Application Number:
20170194343
A semiconductor device that has a split gate charge trapping memory cell having select and memory gates of different heights is presented herein. In an embodiment, the semiconductor device also has a low voltage transistor and a high voltage transistor. In one embodiment, the gates of the transistors are the same height as the select gate. In another embodiment, the gates of the transistors are the same height as the memory gate.
MEMORY TRANSISTOR WITH MULTIPLE CHARGE STORING LAYERS AND A HIGH WORK FUNCTION GATE ELECTRODE
Granted: June 29, 2017
Application Number:
20170186883
Semiconductor devices including non-volatile memory transistors and methods of fabricating the same to improve performance thereof are provided. In one embodiment, the memory transistor comprises an oxide-nitride-oxide (ONO) stack on a surface of a semiconductor substrate, and a high work function gate electrode formed over a surface of the ONO stack. Preferably, the gate electrode comprises a doped polysilicon layer, and the ONO stack comprises multi-layer charge storing layer including…
