Active Stylus to Host Data Transmitting Method
Granted: March 5, 2015
Application Number:
20150062094
Apparatus and methods of active stylus to host device data transmitting are described. One method receives, at a stylus, an indication that a host device is performing a first coordinate measurement operation to determine a coordinate of the stylus proximate to a capacitive sense array of the host device. The set of coordinate measurement operations includes a first measurement operation of a first set of electrodes of the capacitive sense array and a second measurement operation of a…
METHODS OF FABRICATING AN F-RAM
Granted: January 1, 2015
Application Number:
20150004718
Non-volatile memory cells including complimentary metal-oxide-semiconductor transistors and embedded ferroelectric capacitor and methods of forming the same are described. In one embodiment, the method includes forming on a surface of a substrate a gate level including a gate stack of a MOS transistor, a first dielectric layer overlying the MOS transistor and a first contact extending through the first dielectric layer from a top surface thereof to a diffusion region of the MOS…
SONOS Stack With Split Nitride Memory Layer
Granted: December 25, 2014
Application Number:
20140374813
A semiconductor device and method of manufacturing the same are provided. In one embodiment, semiconductor device includes a first oxide layer overlying a channel connecting a source and a drain formed in a substrate, a first nitride layer overlying the first oxide layer, a second oxide layer overlying the first nitride layer and a second nitride layer overlying the second oxide layer. A dielectric layer overlies the second nitride layer and a gate layer overlies the dielectric layer.…
SYSTEMS AND METHODS FOR PROVIDING HIGH VOLTAGE TO MEMORY DEVICES
Granted: December 18, 2014
Application Number:
20140369136
Apparatus, systems, and methods for providing high voltage to memory devices are provided. One apparatus includes a low voltage input and a two-rail level shifting. The two-rail level shifting is configured to increase the low voltage or to decrease the low voltage to an amount that is less than or equal to a ground potential based on the amount of the low voltage. A system includes a low voltage input for receiving a voltage and a two-rail level shifting coupled to the low voltage…
OVER-VOLTAGE TOLERANT CIRCUIT AND METHOD
Granted: December 18, 2014
Application Number:
20140368960
Over-voltage tolerant circuits and methods are provided. In one embodiment, the circuit includes a pull-up transistor coupled to an I/O pad, a sensing circuit coupled to the I/O pad and to a voltage supply (Vcc), the sensing circuit configured to sense a voltage applied to the pad (Vpad), a latch coupled to the sensing circuit to retain an output of the sensing circuit, and a selection circuit coupled to the sensing circuit through the latch. The selection circuit includes a first bias…
ACCESS METHODS AND CIRCUITS FOR MEMORY DEVICES HAVING MULTIPLE BANKS
Granted: November 20, 2014
Application Number:
20140340978
A method can include storing a plurality of addresses within one cycle of a timing clock, each address corresponding to a storage location of a memory device; and following the one cycle, accessing a plurality of banks of the memory device in response to the stored addresses corresponding to different banks and preventing access to any one of the plurality of banks by more than one address of the one cycle; wherein each bank includes memory cells arranged into rows and columns that…
ZERO POWER METERING CIRCUITS, SYSTEMS AND METHODS
Granted: November 6, 2014
Application Number:
20140327553
A system can include a passive wireless interface circuit that generates data from a wireless signal and further includes an energy harvesting circuit that generates first operating power from the wireless signal; a meter interface circuit configured to receive at least one input signal and second operating power from a metering device; logic circuits configured to arbitrate accesses to nonvolatile storage circuits from the passive wireless interface and meter interface circuits using…
Method to Reduce Program Disturbs in Non-Volatile Memory Cells
Granted: October 9, 2014
Application Number:
20140301139
A non-volatile memory and methods of operating the same to reduce disturbs is provided. In one embodiment, the method includes coupling a first positive high voltage to a first global wordline in a first row of an array of memory cells, and coupling a second negative high voltage (VNEG) to a first bitline in a first column of the array to apply a bias to a non-volatile memory transistor in a selected memory cell to program the selected memory cell. A margin voltage having a magnitude…
MEMORY DEVICES AND METHODS FOR HIGH RANDOM TRANSACTION RATE
Granted: October 2, 2014
Application Number:
20140293717
A memory device can include a random access memory array configured to store data values; a plurality of bi-directional ports, configured to transfer data values into and out of the memory device on rising and falling transitions of at least one access clock signal; and at least one address bus configured to receive at least a portion of address values to random access locations on rising and falling transitions a timing clock signal having the same frequency as the access clock signal.
Predictive Touch Surface Scanning
Granted: September 25, 2014
Application Number:
20140285469
A method for locating a conductive object at a touch-sensing surface may include detecting a first resolved location for the conductive object at the touch-sensing surface based on a first scan of the touch-sensing surface, predicting a location for the conductive object, and determining a second resolved location for the conductive object by performing a second scan of a subset of sensor electrodes of the touch-sensing surface, wherein the subset of sensor electrodes is selected based…
Method and Apparatus for Identification of Touch Panels
Granted: September 25, 2014
Application Number:
20140285467
A method for configuring a touchscreen controller may include identifying a model of a touchscreen by measuring a capacitance or resistance of at least one element integrated in the touchscreen, identifying the model of the touchscreen based on the measured capacitance or resistance, and configuring the touchscreen controller based on the identified model of the touchscreen.
OXIDE-NITRIDE-OXIDE STACK HAVING MULTIPLE OXYNITRIDE LAYERS
Granted: September 25, 2014
Application Number:
20140284696
A method of fabricating a memory device is described. Generally, the method includes: forming a tunneling layer on a substrate; forming on the tunneling layer a multi-layer charge storing layer including at least a first charge storing layer comprising an oxygen-rich oxynitride overlying the tunneling layer, and a second charge storing layer overlying the first charge storing layer comprising a silicon-rich and nitrogen-rich oxynitride layer that is oxygen-lean relative to the first…
MEMORY DEVICES AND SYSTEMS INCLUDING MULTI-SPEED ACCESS OF MEMORY MODULES
Granted: September 18, 2014
Application Number:
20140281200
A system, comprising: a plurality of modules, each module comprising a plurality of integrated circuits devices coupled to a module bus and a channel interface that communicates with a memory controller, at least a first module having a portion of its total module address space composed of first type memory cells having a first maximum access speed, and at least a second module having a portion of its total module address space composed of second type memory cells having a second maximum…
DIGITAL DRIVING CIRCUITS, METHODS AND SYSTEMS FOR LIQUID CRYSTAL DISPLAY DEVICES
Granted: September 18, 2014
Application Number:
20140267216
A method may include generating display driver signals that vary between only two levels and applying the display driver signals to opposing electrodes of a display segment within a display device. An intrinsic capacitance of the display device filters the display driver signals to generate different analog signal levels at the display segment of the display device. The method varies the pulse density of the display driver signals to select or de-select the display segment based on an…
ATTENUATOR CIRCUIT OF A CAPACITANCE-SENSING CIRCUIT
Granted: September 18, 2014
Application Number:
20140267151
Apparatuses and methods of input attenuator circuits are described. One sensing circuit includes an attenuator circuit to receive a signal from an electrode of a sense array. The attenuator circuit is configured to attenuate input current of the signal. The attenuator circuit includes an attenuation matrix including an input terminal to receive the signal and multiple resistors. The attenuation matrix is configured to split the input current into an output current of the attenuation…
METHODS AND CIRCUITS FOR MEASURING MUTUAL AND SELF CAPACITANCE
Granted: September 18, 2014
Application Number:
20140266257
In an example embodiment, an apparatus includes a sensing device. The sensing device includes circuitry configured to sense self-capacitance and circuitry configured to sense mutual-capacitance, each configured to detect capacitance values corresponding to whether an object is proximate to a touch screen. The sensing device is configured to measure a first capacitance value using the self-capacitance circuitry during self-capacitance sensing operations and to measure a second capacitance…
NONVOLATILE MEMORY CELLS AND METHODS OF MAKING SUCH CELLS
Granted: September 18, 2014
Application Number:
20140264552
A memory cell can include at least a first programmable section coupled between a supply node and a first data node; a volatile storage circuit coupled to the first data node; and the programmable section includes a programmable transistor having a first source/drain (S/D) region shared with a first transistor, and a second S/D region shared with a second transistor; wherein the first S/D region has a different dopant diffusion profile than the second S/D region, and the programmable…
MEMORY TRANSISTOR WITH MULTIPLE CHARGE STORING LAYERS AND A HIGH WORK FUNCTION GATE ELECTRODE
Granted: September 18, 2014
Application Number:
20140264551
A memory device is described. Generally, the device includes a memory transistor and a metal oxide semiconductor (MOS) logic transistor. The memory transistor includes: a channel region electrically connecting a source region and a drain region, the channel region comprising polysilicon; an oxide-nitride-nitride-oxide (ONNO) stack disposed above the channel region, the ONNO stack comprising a multi-layer charge-trapping region including an oxygen-rich first nitride layer and an…
Nonvolatile Charge Trap Memory Device Having a Deuterated Layer in a Multi-Layer Charge-Trapping Region
Granted: September 18, 2014
Application Number:
20140264550
A nonvolatile charge trap memory device is described. The device includes a substrate having a channel region. A gate stack is disposed above the substrate over the channel region. The gate stack includes a multi-layer charge-trapping region having a first deuterated layer. The multi-layer charge-trapping region may further include a deuterium-free charge-trapping layer.
EMBEDDED SONOS BASED MEMORY CELLS
Granted: August 28, 2014
Application Number:
20140239374
Memory cells including embedded SONOS based non-volatile memory (NVM) and MOS transistors and methods of forming the same are described. Generally, the method includes: forming a dielectric stack on a substrate, the dielectric stack including a tunneling dielectric on the substrate and a charge-trapping layer on the tunneling dielectric; patterning the dielectric stack to form a gate stack of a NVM transistor of a memory device in a first region of the substrate while concurrently…
