DEVELOPMENT, PROGRAMMING, AND DEBUGGING ENVIRONMENT
Granted: August 28, 2014
Application Number:
20140245263
A method includes receiving hardware description code that generically describes circuitry, and translating the hardware description code into one or more configuration files specific to a programmable system. The method further includes generating program code for a microcontroller of the programmable system based, at least in part, on the hardware description code, and configuring the programmable system to implement the circuitry according to the configuration files and the program…
METHOD OF INTEGRATING A CHARGE-TRAPPING GATE STACK INTO A CMOS FLOW
Granted: August 21, 2014
Application Number:
20140235046
A method of fabricating a memory device is described. Generally, the method includes: forming on a surface of a substrate a dielectric stack including a tunneling dielectric and a charge-trapping layer overlying the tunneling dielectric; forming a cap layer overlying the dielectric stack, wherein the cap layer comprises a multi-layer cap layer including at least a first cap layer overlying the charge-trapping layer, and a second cap layer overlying the first cap layer; patterning the cap…
DEUTERATED FILM ENCAPSULATION OF NONVOLATILE CHARGE TRAP MEMORY DEVICE
Granted: August 14, 2014
Application Number:
20140225116
Nonvolatile charge trap memory devices with deuterium passivation of charge traps and methods of forming the same are described. In one embodiment, the device includes a channel formed from a semiconducting material overlying a surface on a substrate connecting a source and a drain of the memory device. A gate stack overlies the channel, the gate stack comprising a tunneling layer, a trapping layer, a blocking layer, a gate layer; and a deuterated gate cap layer. The gate cap layer has a…
MEMORY CELL ARRAY LATCHUP PREVENTION
Granted: July 31, 2014
Application Number:
20140211547
A memory including current-limiting devices and methods of operating the same to prevent a spread of soft errors along rows in an array of memory cells in the memory are provided. In one embodiment, the method begins with providing a memory comprising an array of a plurality of memory cells arranged in rows and columns, wherein each of the columns is coupled to a supply voltage through one of a plurality of current-limiting devices, Next, each of the plurality of current-limiting devices…
TOUCH SENSOR DEVICE
Granted: July 31, 2014
Application Number:
20140210784
Described herein are capacitance sensing devices and methods for forming such devices. A capacitance sensing device includes a substrate and a plurality of electrodes disposed on an area of the substrate to form an active portion of the device. Each of the plurality of electrodes comprises at least one irregular edge formed along a non-linear path. The touch sensor also includes a first plurality of conductors disposed on the substrate. Each of the first plurality of conductors has an…
STYLUS AND RELATED HUMAN INTERFACE DEVICES WITH DYNAMIC POWER CONTROL CIRCUITS
Granted: July 10, 2014
Application Number:
20140192030
A device comprising a body comprising an elongated housing with at least a first conductive tip formed at a distal end and at least one sense electrode on the body; a capacitance sense circuit disposed within the housing and configured to sense a capacitance of the sense electrode to generate a proximity result in response to contact with a human body; and a signal generator circuit disposed within the housing and configured to activate a position signal in response to the proximity…
Tail Effect Correction for SLIM Pattern Touch Panels
Granted: July 10, 2014
Application Number:
20140192027
Techniques for correcting tail effect are described herein. In an example embodiment, a device comprises a sensor coupled with a processing logic. The sensor is configured to measure a plurality of measurements from a sensor array, where the measurements are representative of a conductive object that is in contact with or proximate to the sensor array. The sensor array comprises RX electrodes and TX electrodes that are interleaved without intersecting each other in a single layer on a…
Touch Identification for Multi-Touch Technology
Granted: July 10, 2014
Application Number:
20140191995
A first plurality of contact locations may be determined in view of a first scan of a touch-sensing surface and a second plurality of contact locations may be determined in view of a second scan of the touch-sensing surface. A number of total contact locations may be identified in view of the first plurality of contact locations and the second plurality of contact locations. Furthermore, a first correlation process may be performed when the number of total contact locations satisfies a…
SYSTEM AND METHOD FOR CONTROLLING A LIGHT EMITTING DIODE FIXTURE
Granted: July 10, 2014
Application Number:
20140191675
One embodiment in accordance with the invention can include a circuit for controlling a light emitting diode (LED) lighting fixture via a power line. The circuit can include a power switch coupled to the power line and is for outputting a firing angle. Additionally, the circuit can include a control circuit coupled to the power switch and is for implementing firing angle control of the power switch. Furthermore, the circuit can include a translator coupled to receive the firing angle and…
LOAD DRIVER
Granted: July 3, 2014
Application Number:
20140184280
A method of driving an output terminal to a voltage, in which an input signal is received, an appropriate output voltage and output voltage range are determined based on the input signal, an output driver is configured to a first mode and the output driver drives the output terminal to a voltage within the voltage range, the output driver is configured to a second mode and the output driver drives the output terminal to a voltage approximately equal to the appropriate output voltage.
SENSOR SYSTEM AND METHOD FOR MAPPING AND CREATING GESTURES
Granted: June 12, 2014
Application Number:
20140160030
A computing system includes a sensor configured to detect user inputs. The system further includes a processor configured to receive a detected first user input from the sensor. The processor further receives a detected second user input from the sensor. In response, the processor assigns a command to the first user input based on the second user input.
SONOS TYPE STACKS FOR NONVOLATILE CHANGETRAP MEMORY DEVICES AND METHODS TO FORM THE SAME
Granted: April 17, 2014
Application Number:
20140103418
A method for fabricating a nonvolatile charge trap memory device is described. The method includes forming a first oxide layer on a surface of a substrate. The first oxide layer is exposed to a first decoupled plasma nitridation process having a first bias. Subsequently, a charge-trapping layer is formed on the first oxide layer. The charge-trapping layer is exposed to an oxidation process and then to a second decoupled plasma nitridation process having a second, different, bias.
MEMORY CELL ARRAY LATCHUP PREVENTION
Granted: April 10, 2014
Application Number:
20140098598
A current-limiting device may be configured to be placed along a power-supply bus to limit current through a first complimentary-metal-oxide semiconductor (CMOS) circuit coupled to the power-supply bus so that current does not exceed a trigger current level of a pnpn diode in a second CMOS circuit coupled to the power bus.
MICROCONTROLLER PROGRAMMABLE SYSTEM ON A CHIP WITH PROGRAMMABLE INTERCONNECT
Granted: April 3, 2014
Application Number:
20140095757
Embodiments of the present invention are directed to a microcontroller device having a microprocessor, programmable memory components, and programmable analog and digital blocks. The programmable analog and digital blocks are configurable based on programming information stored in the memory components. Programmable interconnect logic, also programmable from the memory components, is used to couple the programmable analog and digital blocks as needed. The advanced microcontroller design…
DEVELOPMENT, PROGRAMMING, AND DEBUGGING ENVIRONMENT
Granted: April 3, 2014
Application Number:
20140095120
A method includes providing a design interface to design a device schematic for a programmable device and receiving a placement of graphical objects in the device schematic, wherein the graphical objects represent components that are both internal and external to the programmable device being configured. The method further includes assigning the graphical objects into one of an internal domain and an external domain and displaying, by the processing device, the graphical objects from…
METHOD FOR FABRICATING A DAMASCENE SELF-ALIGNED FERRORELECTRIC RANDOM ACCESS MEMORY (F-RAM) HAVING A FERROELECTRIC CAPACITOR ALIGNED WITH A THREE DIMENSIONAL TRANSISTOR STRUCTURE
Granted: April 3, 2014
Application Number:
20140093983
A method for a non-volatile, ferroelectric random access memory (F-RAM) device that includes a ferroelectric capacitor aligned with a preexisting structure is described. In one embodiment, the method includes forming an opening in an insulating layer over a contact in a planar surface of a substrate to expose at least a portion of the contact. Next a self-aligned contact (SAC) is formed electrically coupling to the contact, the SAC medially located in the opening and proximal to a…
METHOD FOR FABRICATING A DAMASCENE SELF-ALIGNED FERRORELECTRIC RANDOM ACCESS MEMORY (F-RAM) WITH SIMULTANEOUS FORMATION OF SIDEWALL FERROELECTRIC CAPACITORS
Granted: March 27, 2014
Application Number:
20140087484
A method for fabricating a non-volatile, ferroelectric random access memory (F-RAM) device is described. In one embodiment, the method includes forming an opening in an insulating layer over a surface of a substrate, and forming bottom electrode spacers proximal to sidewalls of the opening. Next, a ferroelectric dielectric layer is formed in the opening over the surface of the substrate and between the bottom electrode spacers, and a pair of top electrodes is formed within the opening…
CAPACITIVE STYLUS FOR A TOUCH SCREEN
Granted: March 27, 2014
Application Number:
20140085257
A stylus having a transmit drive circuit configured to transmit a signal to a capacitance sensor via capacitive coupling between the stylus and a capacitive sense array which is coupled to the capacitance sensor, which is configured to synchronize to the stylus, the stylus being configured to act as a timing master.
METHOD FOR IMPROVING SCAN TIME AND SENSITIVITY IN TOUCH SENSITIVE USER INTERFACE DEVICE
Granted: March 20, 2014
Application Number:
20140077827
System and method for optimizing the consumption of power while maintaining performance in capacitive sensor arrays. A limited sensing area is used to improve the update rate and sensitivity of a row/column array of capacitive sensors. According to one embodiment, a method is provided for scanning a plurality of capacitive sensors by: detecting a stimulus in the field of capacitive sensors, scanning the field of capacitive sensors to determine the position of the stimulus. Once the…
ACCESS METHODS AND CIRCUITS FOR MEMORY DEVICES HAVING MULTIPLE BANKS
Granted: February 27, 2014
Application Number:
20140056093
A method can include storing bank addresses, if received, on at least rising and falling edges of a same clock cycle; and if addresses stored on the rising and falling edges of the same clock cycle correspond to different banks of a memory device, starting accesses to both banks after the falling edge of the clock cycle; wherein any of the banks can be accessed in response to an address stored on a rising edge of a next clock cycle. Devices and additional methods are also disclosed.
