Frequency offset and method of offsetting
Granted: May 3, 2007
Application Number:
20070098111
A transmitter digital signal processor (DSP) circuit has a transmit frequency represented by n-bit data output from a look up table (LUT). The n-bit data is outputted to an n-bit accumulator structured to overflow at a rate based on the output n-bit data to output a phase. The circuit further has device structured to add an n-bit signed constant to the accumulator to offset the frequency represented by the n-bit data output from the LUT. A transceiver on a semiconductor chip may include…
METHOD AND APPARATUS FOR SCANNING A KEY OR BUTTON MATRIX
Granted: May 3, 2007
Application Number:
20070096949
An improved key matrix scanning technique conducts a first pre-scan on a first array of connections in a key matrix to identify any activated keys or buttons associated with the first array. A second sub-scan is conducted on a second array of connections in the key matrix but only for the connections in the first array that are detected as having activated keys.
TRI-STATING A PHASE LOCKED LOOP TO CONSERVE POWER
Granted: April 12, 2007
Application Number:
20070082635
In a system with an intermittently operating radio, the frequency of which is controlled by a Phase Locked Loop (PLL), a method and system for reducing the power consumed by the PLL by tri-stating the control capacitor in the PLL after the PLL has stabilized at a design frequency. After the capacitor is stabilized, power to some of the components in the PLL is reduced.
METHOD FOR CHANNEL AGILITY IN WIRELESS ACCESS POINTS
Granted: April 5, 2007
Application Number:
20070076657
A system and method comprising automatically detecting signal activity associated with a frequency band having a plurality of channels for wireless communication, automatically identifying at least one channel having a low level of signal activity relative to one or more other channels associated with the frequency band, and selecting at least one of the identified channels for communicating over the frequency band.
Simplified universal serial bus (USB) hub architecture
Granted: April 5, 2007
Application Number:
20070079045
A Universal Serial Bus (USB) device uses a same elasticity buffer for buffering packets for multiple different ports and only necessary packet detection circuitry is associated with the individual ports. A collision detection circuit is further included corresponding with information received from the packet detection circuitry. This simplified universal elasticity buffer architecture reduces the complexity and cost of the USB device.
REDUCING THE SETTLING TIME OF A CRYSTAL OSCILLATOR
Granted: March 29, 2007
Application Number:
20070069829
A method and system for initiating the oscillation of a crystal that controls a crystal oscillator by applying an initiating pulse to said crystal. The initiating pulse having a pulse width less than one half the periodicity of said crystal.
APPARATUS AND METHOD FOR CALIBRATING MIXER OFFSET
Granted: March 29, 2007
Application Number:
20070069928
A circuit including a subcircuit having differential signals, and a feedback circuit coupled to the subcircuit. The feedback circuit is configured to measure an offset between the differential signals, to generate a calibration signal in response to the measurement, and to reduce the offset in response to the calibration signal.
Circuit, System, and Method for Multiplexing Signals with Reduced Jitter
Granted: March 8, 2007
Application Number:
20070053475
A multiplexer circuit, system and method is provided herein for multiplexing signals with reduced jitter by eliminating all crosstalk and power supply noise injection within the multiplexer circuit. For example, crosstalk and supply noise injection may be eliminated by: (i) separating the multiplexing function into three separate logic gates and (ii) allowing only one switching input per logic gate. In some cases, jitter may be further reduced by distributing the logic gates across three…
CIRCUIT FOR CREATING TRACKING TRANSCONDUCTORS OF DIFFERENT TYPES
Granted: March 1, 2007
Application Number:
20070046368
Systems and method for tracking different types of transconductance cells is shown and described. In these multi-cell systems, the addition of one or more tracking control modules allows circuit designers to advantageously incorporate multiple transconductor topologies and their uniquely beneficial characteristics into their designs, without eradicating its centralized multi-cell tuning functionality.
FLASH DRIVE FAST WEAR LEVELING
Granted: March 1, 2007
Application Number:
20070050536
A system and method comprising a non-volatile memory including one or more memory blocks to store data, a controller to allocate one or more of the memory blocks to store data, and a wear-leveling table populated with pointers to unallocated memory blocks in the non-volatile memory, the controller to identify one or more pointers in the wear-leveling table and to allocate the unallocated memory blocks associated with the identified pointers for the storage of data.
Regulated Capacitive Loading and Gain Control of a Crystal Oscillator During Startup and Steady State Operation
Granted: February 8, 2007
Application Number:
20070030085
An oscillator circuit and system are provided having a peak detector that can determine a peak voltage value from the oscillator. The peak voltage value can then be compared against a predetermined voltage value by a controller coupled to the peak detector. The comparison value is then used to change a bias signal if the peak voltage value is dissimilar from the predetermined voltage value. A variable capacitor or varactor can be formed from a transistor and is coupled to the oscillator…
CIRCUIT AND METHOD FOR SELECTABLE HIGH/LOW SIDE INJECTION IN AN INTERMEDIATE FREQUENCY TRANSCEIVER
Granted: January 4, 2007
Application Number:
20070004370
A method of communication between a first transceiver having a first local oscillator set at a first frequency and a second transceiver having a second local oscillator set at a second frequency disclosed. The method includes transmitting a first signal at a first frequency from the first transceiver to the second transceiver, transmitting a second signal at the second frequency from the second transceiver to the first transceiver, and receiving the second signal at the first…
EARLY DETECTION AND GRANT, AN ARBITRATION SCHEME FOR SINGLE TRANSFERS ON AMBA ADVANCED HIGH-PERFORMANCE BUS
Granted: December 21, 2006
Application Number:
20060288143
A bus architecture includes master devices that are each capable of initiating a data transfer procedure by generating a bus request signal. Each of the master devices is arranged to transmit an address signal to an address input of a multiplexer, to transmit a data signal to a data input of the multiplexer, and to transmit a control signal to a control input of the multiplexer. The control signals may include burst type control signals. The multiplexer is capable of selectively coupling…
Directional capacitive sensor system and method
Granted: October 26, 2006
Application Number:
20060238205
A capacitive sensing system (200) can include a sense section (202) and a filter section (206). Sense section (202) can activate logic outputs based on a sensed capacitance from sensors (210-1 and 210-2). A filter section (206) can logically combine logic outputs in different ways to generate output signals (INT—1 and INT—2). According to output signals (INT—1 and INT—2), different types of movement in a capacitive body (212) can be detected.
One time programmable latch and method
Granted: June 1, 2006
Application Number:
20060114020
A one-time programmable (OTP) latch circuit can include a single OTP device capable of storing a logic value in a nonvolatile fashion, or only two OTP devices in the event redundancy is desired. A latch section can latch a data value based on a comparison between a current drawn according to the one OTP device, and a reference current generated without and OTP device. An OTP device can include a gate oxide antifuse (GOAF) device.
Dual damascene structure and method of making
Granted: September 23, 2004
Application Number:
20040183199
A dual damascene interconnect structure, produced using etch chemistry based on C2H2F4, includes (i) an etch stop layer of either undoped silicon oxide or doped silicon oxide, and (ii) dielectric layers both above and below the etch stop layer of the other (i.e., when the etch stop layer comprises undoped silicon oxide, the dielectric layers above and below the etch stop layer independently comprise a doped silicon oxide; and when the etch stop layer comprises doped silicon oxide, the…
Method of making metallization and contact structures in an integrated circuit using a timed trench etch
Granted: April 29, 2004
Application Number:
20040082182
The invention concerns a method for forming metallization and contact structures in an integrated circuit. The method involoves the steps of etching a trench in the trench dielectric layer a trench dielectric layer of a composite structure containing a semiconductor substrate comprising an active region, a gate structure thereover, and dielectric spacers adjacent to the gate structure, a contact dielectric layer; and the trench dielectric layer; etching the contact dielectric layer under…
Planarized semiconductor interconnect topography and method for polishing a metal layer to form wide interconnect structures
Granted: November 27, 2003
Application Number:
20030219975
The present invention advantageously provides a substantially planarized semiconductor topography and method for making the same by selectively etching a dielectric layer to form a plurality of posts surrounded by trenches. The trenches are filled with a conductive material, such as a metal, deposited to a level spaced above the upper surfaces of the dielectric layer and the posts. The surface of the conductive material is then polished to a level substantially coplanar with the upper…
Method and architecture for self-clocking digital delay locked loop
Granted: May 1, 2003
Application Number:
20030080791
An apparatus comprising a delay line and a control circuit. The delay line may be configured to generate an output signal in response to an input signal and one or more control signals. The delay line may be self-clocked. A phase of the output signal may be adjusted in response to the one or more control signals. The control circuit may be configured to generate the one or more control signals in response to the input signal and the output signal.
Digitally controlled analog delay locked loop (DLL)
Granted: February 6, 2003
Application Number:
20030025539
An apparatus comprising an analog delay line and a control circuit. The analog delay line may be configured to generate an output signal in response to an input signal, a first control signal, and a second control signal. A phase of the output signal may be (i) coarsely adjustable with respect to the input signal in response to the first control signal and (ii) finely and continuously adjustable in response to the second control signal. The control circuit may be configured to generate…
