Cypress Semiconductor Patent Applications

Proportional to temperature voltage generator

Granted: December 26, 2002
Application Number: 20020196692
A biasing circuit comprising a first circuit and a second circuit. The first circuit may be configured to generate a first bias signal and a second bias signal. The second bias signal may be defined by a threshold voltage and a first resistance. The second circuit may be configured to generate a third bias signal in response to the first and the second bias signals and a second resistance. The third bias signal may have a magnitude that is linearly proportional to absolute temperature…

Substrate isolated transistor

Granted: December 26, 2002
Application Number: 20020197820
A device and a method are provided for isolating a circuit well from a substrate of the same conductivity type. In particular, an integrated circuit is provided which includes a circuit well arranged over a semiconductor substrate with no layer of opposite conductivity type arranged between the well and the substrate. The integrated circuit may further include a pair of isolation wells extending along opposite lateral boundaries of the circuit well. The isolation wells and circuit well…

Programmable protocol processing engine for network packet devices

Granted: December 19, 2002
Application Number: 20020191621
A circuit generally comprising a database and a processing circuit. The database may be configured to store a pointer for each first parameter of a network protocol. The processing circuit may be configured to (i) process at least one of the first parameters in an incoming packet in accordance with the pointer to produce a second parameter and (ii) present an outgoing packet containing the second parameter.

Programmable protocol processing engine for network packet devices

Granted: December 19, 2002
Application Number: 20020194363
A method of bridging an incoming packet from a first network to a second network. The method may comprise the steps of (A) reading a pointer for a first parameter within the incoming packet, (B) processing the first parameter in accordance with the pointer to produce a second parameter, and (C) presenting an outgoing packet containing the second parameter for the second network in response to step (B).

Active termination circuit with an enable/disable

Granted: October 17, 2002
Application Number: 20020149390
A termination circuit for use on a conductor of a transmission line. The termination circuit generally comprises a first, second, third and fourth transistor. The first transistor may have (i) a first drain node couplable to the conductor, (ii) a first source node couplable to a first power source presenting a first reference voltage, and (iii) a first gate node. The second transistor may have (i) a second drain node couplable to the conductor, (ii) a second source node couplable to a…

MOS transistor with ramped gate oxide thickness and method for making same

Granted: October 10, 2002
Application Number: 20020145166
The invention relates to a transistor having a ramped gate oxide thickness, a semiconductor device containing the same and a method for making a transistor.

Method for selectively etching silicon and/or metal silicides

Granted: October 3, 2002
Application Number: 20020142596
A metal silicide (e.g., WSix) layer an integrated circuit is etched in a Cl2/O2 environment having an O2 concentration of greater than or equal to 25% by volume. This environment may be provided at a pressure of approximately 2-40 mili-Torr, in a reactor with a source power of approximately 200-2000 Watts and a bias power of approximately 30-400 Watts for approximately 30 seconds. In one particular example, the Cl2/O2 environment includes approximately 45 sccm Cl2 and 30 sccm O2. The…

Method for reducing power consumption in a universal serial bus device

Granted: October 3, 2002
Application Number: 20020144165
The present invention concerns a method for reducing power consumption in a device, comprising the steps of (A) receiving one or more packets, (B) determining a type of each of the one or more packets and (C) suspending, waking, or partially waking the device in response to a particular type of packet.

Follow-up notification of availability of requested application service and bandwidth between client (s) and server (s) over any network

Granted: September 26, 2002
Application Number: 20020138613
A method for providing orderly service delivery to clients over a network, comprising the steps of (A) requesting data from a location and (B) if a denial is received, notifying a particular client of availability.

Configurable and memory architecture independent memory built-in self test

Granted: September 19, 2002
Application Number: 20020133768
A circuit that may be used to support testing of a memory block. The circuit generally comprises a decoder and a generator. The decoder may be configured to (i) decode a command signal into an address field, an operation field, and a data field and (ii) present a control signal to the memory block in response to the operation field. The generator may be configured to (i) present an address signal to the memory block in response to the address field and (ii) present a data signal to the…

Method for selectively etching silicon and/or metal silicides

Granted: July 11, 2002
Application Number: 20020090817
A metal silicide (e.g., WSix) layer an integrated circuit is etched in a Cl2/O2 environment having an O2 concentration of greater than or equal to 25% by volume. This environment may be provided at a pressure of-approximately 2-40 mili-Torr, in a reactor with a source power of approximately 200-2000 Watts and a bias power of approximately 30-400 Watts for approximately 30 seconds. In one particular example, the Cl2/O2 environment includes approximately 45 sccm Cl2 and 30 sccm O2. The…

Automatic documentation generation tool and associated method

Granted: May 16, 2002
Application Number: 20020059348
The invention relates to an automatic documentation tool and associated method. The method includes embedding comments into a plurality of source files defining the design, creating a configuration file including parameters associated with each source file, and extracting the comments from each source file responsive to the parameters. The method is capable of operating on a plurality of source files originating from a plurality of design tools. The method is capable of sorting through…

Synchronous burst memory

Granted: December 13, 2001
Application Number: 20010052045
A device generally comprising a memory array and a burst sequence generator. The memory array may be configured to store data. The burst sequence generator may be configured to generate a burst sequence in response to address information received by the device. The burst sequence may be configured to identify a plurality of locations for storing data in the memory array. The device may have a maximum operating current of 50 milliamps and/or a maximum standby current of about 25…

Method of forming metal layer(s) and/or antireflective coating layer(s) on an integrated circuit

Granted: July 19, 2001
Application Number: 20010008793
A method of forming metallic layers on a substrate includes the steps of forming a first layer including a first metal on the substrate; cooling the first layer for a period of time sufficient to suppress formation of an intermetallic phase; and forming a second layer including a second metal distinct from the first metal on the first layer. The cooling step decreases the roughness of the resultant stacked structure by suppressing the formation of an intermetallic phase layer between the…

Circuit, architecture and method for reducing power consumption in a synchronous integrated circuit

Granted: May 10, 2001
Application Number: 20010000995
An apparatus comprising a circuit configured to automatically generate a sleep signal upon detecting that one or more chip select signals has been in a first state for a predetermined number of clock cycles.