Sensor-compatible overlay
Granted: May 7, 2019
Patent Number:
10282585
A fingerprint sensor-compatible overlay material which uses anisotropic conductive material to enable accurate imaging of a fingerprint through an overlay is disclosed. The anisotropic conductive material has increased conductivity in a direction orthogonal to the fingerprint sensor, increasing the capacitive coupling of the fingerprint to the sensor surface, allowing the fingerprint sensor to accurately image the fingerprint through the overlay. Methods for forming a fingerprint…
Radical oxidation process for fabricating a nonvolatile charge trap memory device
Granted: April 23, 2019
Patent Number:
10269985
A memory device is described. Generally, the memory device includes a tunnel oxide layer overlying a channel connecting a source and a drain of the memory device formed in a substrate, a multi-layer charge storing layer overlying the tunnel oxide layer and a high-temperature-oxide (HTO) layer overlying the multi-layer charge storing layer. The multi-layer charge storing layer includes an oxygen-rich, first layer comprising a nitride on the tunnel oxide layer in which a composition of the…
Capacitive fingerprint sensor with quadrature demodulator and multiphase scanning
Granted: April 23, 2019
Patent Number:
10268867
A method includes providing a differential signal and generating an in-phase component of the differential signal and a quadrature component of the differential signal. The method further includes generating an output signal representing a capacitance value using the in-phase component and the quadrature component.
Nonvolatile charge trap memory device having a deuterated layer in a multi-layer charge-trapping region
Granted: April 16, 2019
Patent Number:
10263087
A memory is described. Generally, the memory includes a number of non-planar multigate transistors, each including a channel of semiconducting material overlying a surface of a substrate and electrically connecting a source and a drain, a tunnel dielectric layer overlying the channel on at least three sides thereof, and a multi-layer charge-trapping region overlying the tunnel dielectric layer. In one embodiment, the multi-layer charge-trapping region includes a first deuterated layer…
Method to reduce program disturbs in non-volatile memory cells
Granted: April 16, 2019
Patent Number:
10262747
A non-volatile memory that includes a shared source line configuration and methods of operating the same to reduce disturbs is provided. In one embodiment, the method includes coupling a first positive high voltage to a first global wordline in a first row of an array of memory cells, and coupling a second negative high voltage (VNEG) to a first bitline in a first column of the array to apply a bias to a non-volatile memory transistor in a selected memory cell to program the selected…
Microcontroller programmable system on a chip
Granted: April 16, 2019
Patent Number:
10261932
Embodiments of the present invention are directed to a microcontroller device having a microprocessor, programmable memory components, and programmable analog and digital blocks. The programmable analog and digital blocks are configurable based on programming information stored in the memory components. Programmable interconnect logic, also programmable from the memory components, is used to couple the programmable analog and digital blocks as needed. The advanced microcontroller design…
Self-aligned trench isolation in integrated circuits
Granted: April 9, 2019
Patent Number:
10256137
An A method for fabricating an integrated circuit (IC) comprising a substrate, a first device, a second device, and a trench in the substrate is described herein. The trench is self-aligned between the first and second devices and comprises a first portion filled with a dielectric material and a second portion filled with a conductive material. The self-aligned placement of the trench provides electrical isolation between the first and second devices and allows for higher packing density…
Configurable and power-optimized integrated gate-driver for USB power-delivery and type-C SoCs
Granted: April 9, 2019
Patent Number:
10254820
Techniques for power Field Effect Transistor (power-FET) gate drivers are described herein. In an example embodiment, a USB-enabled system comprises a first and second power paths and an IC controller coupled to control the first and second power paths, where the first and second power paths are external to the IC controller and the IC controller is configured to operate both an N-channel power-FET in the first power path and a P-channel power-FET in the second power path.
Low inrush circuit for power up and deep power down exit
Granted: April 9, 2019
Patent Number:
10254812
Systems, methods, and devices for providing power to low energy circuits include inrush circuits. Devices include a regulator that includes at least one driver device configured to generate a first current associated with a load comprising a low energy integrated circuit. Devices also include a bias generator configured to generate a second current to charge a load capacitor coupled with a power terminal of the low energy integrated circuit. Devices further include an enable circuit…
Microcontroller programmable system on a chip
Granted: April 2, 2019
Patent Number:
10248604
Embodiments of the present invention are directed to a microcontroller device having a microprocessor, programmable memory components, and programmable analog and digital blocks. The programmable analog and digital blocks are configurable based on programming information stored in the memory components. Programmable interconnect logic, also programmable from the memory components, is used to couple the programmable analog and digital blocks as needed. The advanced microcontroller design…
Method of forming high-voltage transistor with thin gate poly
Granted: March 26, 2019
Patent Number:
10242996
A semiconductor device and method of fabricating the same are disclosed. The method includes depositing a polysilicon gate layer over a gate dielectric formed over a surface of a substrate in a peripheral region, forming a dielectric layer over the polysilicon gate layer and depositing a height-enhancing (HE) film over the dielectric layer. The HE film, the dielectric layer, the polysilicon gate layer and the gate dielectric are then patterned for a high-voltage Field Effect Transistor…
Low quiescent current DC-to-DC converter with increased output voltage accuracy
Granted: March 19, 2019
Patent Number:
10236773
Systems and methods for driving a low quiescent current DCDC converter are disclosed. An error threshold compensation circuit of the DCDC converter is configured to detect an output voltage of the DCDC converter, compare the output voltage to a target voltage, and modify a first threshold voltage of the hysteresis control circuit based on the comparison.
Three-dimensional charge trapping NAND cell with discrete charge trapping film
Granted: March 19, 2019
Patent Number:
10236299
A three-dimensional charge trap semiconductor device is constructed with alternating insulating and gate layers stacked over a substrate. During the manufacturing process, a channel hole is formed in the stack and the gate layers are recessed from the channel hole. Using the recessed topography of the gate layers, a charge trap layer can be deposited on the sidewalls of the channel hole and etched, leaving individual discrete charge trap layer sections in each recess. Filling the channel…
Fingerprint sensor-compatible overlay material
Granted: March 19, 2019
Patent Number:
10235558
A fingerprint sensor-compatible overlay material which uses anisotropic conductive material to enable accurate imaging of a fingerprint through an overlay is disclosed. The anisotropic conductive material has increased conductivity in a direction orthogonal to the fingerprint sensor, increasing the capacitive coupling of the fingerprint to the sensor surface, allowing the fingerprint sensor to accurately image the fingerprint through the overlay. Methods for forming a fingerprint…
Suppression of program disturb with bit line and select gate voltage regulation
Granted: March 12, 2019
Patent Number:
10229745
Techniques for suppression of program disturb in flash memory devices are described herein. In an example embodiment, an apparatus comprises a flash memory device coupled to a microprocessor. The flash memory device comprises rows and columns of memory cells, where the memory cells in each row are coupled to a source line and to a select-gate (SG) line, and the memory cells in each column are coupled to a respective bit line (BL). A control circuit in the flash memory device is…
USB power control analog subsystem architecture
Granted: March 12, 2019
Patent Number:
10228742
A device and method that include a power control analog subsystem of a universal serial bus (USB) compatible power supply device is disclosed. The power control analog subsystem includes a programmable reference generator to generate first reference voltages. The power control analog subsystem also includes multiplexers, where each of a plurality of multiplexers are coupled to a first terminal and a second terminal of a producer field-effect transistor (FET) to receive a first voltage…
Current sensing in a USB power control analog subsystem
Granted: March 5, 2019
Patent Number:
10222402
A device includes a power control analog subsystem of a universal serial bus-power delivery (USB-PD) compatible power supply device. The power control analog subsystem includes a programmable current sensing circuit and a current sense resistor coupled to the power control analog subsystem. The power control analog subsystem is configured to concurrently compare a current flow through the current sense resistor with at least three different reference values, e.g., compare a sensed…
Overvoltage protection for universal serial bus type-C (USB-C) connector systems
Granted: February 26, 2019
Patent Number:
10218129
An electronic device includes a first switch configured to connect a first configuration channel (CC) terminal of a Universal Serial Bus Type-C (USB-C) controller to a VCONN supply of the USB-C controller. The first CC terminal of the USB-C controller being is to directly connect to the first CC terminal of a USB-C receptacle. The electronic device includes a second switch configured to connect a second CC terminal of the USB-C controller to a control channel physical layer logic (PHY)…
Method of forming drain extended MOS transistors for high voltage circuits
Granted: February 26, 2019
Patent Number:
10217639
A device including both drain extended metal-on-semiconductor (DE_MOS) and low-voltage metal-on-semiconductor (LV_MOS) transistors and methods of manufacturing the same are provided. In one embodiment, the method includes implanting ions of a first-type at a first energy level in a drain portion of a first DE_MOS transistor in a DE_MOS region of a substrate to form the first DE_MOS transistor, and implanting ions of the first-type at a second energy level in a LV_MOS region of the…
Method to reduce program disturbs in non-volatile memory cells
Granted: February 12, 2019
Patent Number:
10204691
A non-volatile memory that includes a shared source line configuration and methods of operating the same to reduce disturbs is provided. In one embodiment, the method includes coupling a first positive high voltage to a first global wordline in a first row of an array of memory cells, and coupling a second negative high voltage (VNEG) to a first bitline in a first column of the array to apply a bias to a non-volatile memory transistor in a selected memory cell to program the selected…
