Spur cancellation system for modems
Granted: February 5, 2019
Patent Number:
10200070
A modem includes a modulator and a demodulator. The demodulator includes a direct current removing (DCR) circuit to transition between an acquisition mode, where the DCR circuit operates with a first loop gain; and a tracking mode, where the DCR circuit operates with a second loop gain. The second loop gain is smaller than the first loop gain, and the timing of the transition between the acquisition mode and tracking mode is programmable.
SONOS stack with split nitride memory layer
Granted: February 5, 2019
Patent Number:
10199229
A semiconductor device and method of manufacturing the same are provided. In one embodiment, method includes forming a first oxide layer over a substrate, forming a silicon-rich, oxygen-rich, oxynitride layer on the first oxide layer, forming a silicon-rich, nitrogen-rich, and oxygen-lean nitride layer over the oxynitride layer, and forming a second oxide layer on the nitride layer. Generally, the nitride layer includes a majority of charge traps distributed in the oxynitride layer and…
Multi-layer inter-gate dielectric structure and method of manufacturing thereof
Granted: January 29, 2019
Patent Number:
10192747
A semiconductor device having a first gate stack on a substrate is disclosed. The first gate stack may include a first gate conductor over a first gate dielectric structure. A dielectric structure can be formed over the first gate stack and the substrate. The dielectric structure layer can include four or more layers of two or more dielectric films disposed in an alternating manner. The dielectric structure can be selectively etched to form an inter-gate dielectric structure. A second…
Non-volatile memory array with memory gate line and source line scrambling
Granted: January 29, 2019
Patent Number:
10192627
A memory device includes a memory array arranged in rows and columns. The memory array may have at least four non-volatile memory (NVM) cells coupled in the same column of the memory array, in which each NVM cell may include a memory gate. The first and second NVM cells of the at least four NVM cells may share a first source region, and the third and fourth NVM cells may share a second source region. The memory gates of the first and second NVM cells may not be electrically coupled with…
Systems, methods, and apparatus for memory cells with common source lines
Granted: January 29, 2019
Patent Number:
10192622
A method for operating a memory device includes the steps of providing a first voltage to a first transistor of a first memory cell and a third transistor of a second memory cell, providing a second voltage to a gate of a second transistor of the first memory cell and a gate of a fourth transistor of the second memory cell, and providing a third voltage to a gate of the first transistor of the first memory cell and a gate of the third transistor of the second memory cell. Other…
Encryption for XIP and MMIO external memories
Granted: January 29, 2019
Patent Number:
10192062
Techniques for multiplexing between an execute-in-place (XIP) mode and a memory-mapped input/output (MMIO) mode for access to external memory devices are described herein. In an example embodiment, an IC device comprises a serial interface and a controller that is configured to communicate with external memory devices over the serial interface. The controller comprises a control register and a cryptography block. The control register is configured to indicate an XIP mode or a MMIO mode.…
Low-power Type-C receiver with high idle noise and DC-level rejection
Granted: January 29, 2019
Patent Number:
10191524
Techniques for low-power USB Type-C receivers with high DC-level shift tolerance are described herein. In an example embodiment, a USB-enabled device comprises a receiver circuit coupled to a Configuration Channel (CC) line of a USB Type-C subsystem. The receiver circuit is configured to receive data from an incoming signal on the CC line even when the incoming signal has more than 250 mV of DC offset with respect to local ground, and to operate in presence of a VBUS charging current…
Pressure detection and measurement with a fingerprint sensor
Granted: January 22, 2019
Patent Number:
10185867
A circuit, system, and method for measuring or detecting pressure or force of a fingerprint on an array of electrodes is described. Pressure or force may be measured or detected using a processed image of the fingerprint, or by measurement of capacitance of deformed variable capacitors.
Uniformity correction method for low cost and non-rectangular touch sensor matrices
Granted: January 22, 2019
Patent Number:
10185444
A method includes storing a set of touch sense values corresponding to a measured characteristic of at least one unit cell of a plurality of unit cells of the touch array and accessing a correction matrix that defines an active region and an inactive region of the touch array. The inactive region is surrounded by the active region. The method further includes modifying touch sense values of a first subset of the plurality of unit cells that are partially within the active region defined…
Manufacturing of FET devices having lightly doped drain and source regions
Granted: January 8, 2019
Patent Number:
10177040
Embodiments described herein generally relate to methods of manufacturing n-type lightly doped drains and p-type lightly doped drains. In one method, photoresist mask is used to etch a transistor, and the mask is left in place (i.e., reused) to protect other devices and poly while a high energy implantation is performed in alignment with the photoresist mask, such that the implantation is adjacent to the etched transistor. One example of a high energy implantation is forming lightly…
Encryption method for execute-in-place memories
Granted: January 1, 2019
Patent Number:
10169618
Encryption/decryption techniques for external memory are described herein. In an example embodiment, a device comprises an internal memory and an external memory controller. The internal memory is configured to store a key. The external memory controller is configured to encrypt, with the key, an address for an access operation to an external memory device to obtain an encrypted address, and to encrypt or decrypt a block of data for the access operation based on the encrypted address.
Dynamically switching communication modes in multi-standard wireless communication devices
Granted: December 25, 2018
Patent Number:
10165425
Techniques for wireless communications are described. In an example embodiment, a method of configuring wireless communication between two devices comprises using two different communication channels each having a different number of timeslots, in which the first channel is used in a first mode, the second channel is used in the second mode, and operation transitions between the first mode and the second mode in accordance with a predetermined characteristic corresponding to the…
Ratiometric mutual-capacitance-to-code converter
Granted: December 25, 2018
Patent Number:
10162467
An embodiment of a capacitance sensing circuit includes a set of bridge switches coupled with a reference cell and a sensor cell. The set of bridge switches is configured to, over a first phase, increase a voltage difference between a first modulation capacitor and a second modulation capacitor, and over a second phase, decrease the voltage difference at a rate corresponding to a difference between a capacitance of the sensor cell and a capacitance of the reference cell. The capacitance…
Encryption for XIP and MMIO external memories
Granted: December 18, 2018
Patent Number:
10157283
Techniques for multiplexing between an execute-in-place (XIP) mode and a memory-mapped input/output (MMIO) mode for access to external memory devices are described herein. In an example embodiment, an IC device comprises a serial interface and a controller that is configured to communicate with external memory devices over the serial interface. The controller comprises a control register and a cryptography block. The control register is configured to indicate an XIP mode or a MMIO mode.…
Programmable input/output circuit
Granted: December 11, 2018
Patent Number:
10153770
A apparatus, having a processing system and an input buffer coupled with both the processing system and one of two IO pads, and a reference buffer coupled to both the input buffer and the second of the IO pads such that the reference generator controls the input threshold of the input buffer in response to an analog voltage received from an external circuit on the second of the IO pads.
Method of ONO stack formation
Granted: December 11, 2018
Patent Number:
10153294
A method of controlling the thickness of gate oxides in an integrated CMOS process which includes performing a two-step gate oxidation process to concurrently oxidize and therefore consume at least a first portion of the cap layer of the NV gate stack to form a blocking oxide and form a gate oxide of at least one metal-oxide-semiconductor (MOS) transistor in the second region, wherein the gate oxide of the at least one MOS transistor is formed during both a first oxidation step and a…
Method of forming controllably conductive oxide
Granted: December 4, 2018
Patent Number:
10147877
In fabricating a memory device, a first electrode is provided. An oxide layer is provided on the first electrode. A second electrode is provided on the oxide layer. In a further method of fabricating a memory device, a first electrode is provided. An oxide layer is provided on the first electrode, the oxide layer comprising an oxygen deficiency and/or defects therein. A second electrode is then provided on the oxide layer.
Memory gate driver technology for flash memory cells
Granted: December 4, 2018
Patent Number:
10147734
A memory array including a first memory cell including a first memory gate coupled to receive a first signal. The memory array including a second memory cell including a first memory gate coupled to receive a second signal. The magnitude of the second signal is different than the magnitude of the first signal. The memory array including a third memory cell including a first memory gate coupled to receive a third signal. The magnitude of the third signal is different than the magnitude of…
Method of combining self and mutual capacitance sensing
Granted: December 4, 2018
Patent Number:
10146390
A capacitance sensing method includes generating a first set of currents by, for each transmit (TX) electrode of a set of TX electrodes, precharging a self capacitance of the TX electrode and a mutual capacitance between the TX electrode and a receive (RX) electrode of a set of RX electrodes by applying to the TX electrode a first excitation voltage corresponding to the TX electrode to induce a first current of the first set of currents, generating a second set of currents by, for each…
Row redundancy with distributed sectors
Granted: November 27, 2018
Patent Number:
10141065
A semiconductor device comprises an embedded flash memory with row redundancy. The embedded flash memory comprises a memory bank that includes multiple physical sectors, where each physical sector comprises a plurality of erase sectors. In the memory bank, multiple portions of an additional erase sector are respectively distributed among the multiple physical sectors. The multiple portions of the additional erase sector are configured as a row-redundancy sector for the memory bank.
