Voltage adjustment circuit and display device driving circuit
Granted: December 19, 2017
Patent Number:
9846321
A voltage adjustment circuit for adjusting a voltage to be supplied to scanning lines of a display device includes a slope adjustment circuit configured to adjust a slope of a decrease in the voltage based on data that is externally input, and a clamp voltage adjustment circuit configured to adjust a voltage value at which the voltage is clamped based on the data.
PSOC architecture
Granted: December 12, 2017
Patent Number:
9843327
A circuit with a plurality of analog circuit blocks, each configured to provide at least one analog function and a programmable interconnect coupled of the analog circuit blocks and configurable to interconnect combinations of the analog circuit blocks to one another. The circuit is formed in an integrated circuit (chip) and the programmable interconnect comprises a plurality of switches coupled between the analog circuit blocks and ports that provide signal connections for the chip.
Memory cell array latchup prevention
Granted: December 12, 2017
Patent Number:
9842629
A memory including current-limiting devices and methods of operating the same to prevent a spread of soft errors along rows in an array of memory cells in the memory are provided. In one embodiment, the method begins with providing a memory comprising an array of a plurality of memory cells arranged in rows and columns, wherein each of the columns is coupled to a supply voltage through one of a plurality of current-limiting devices, Next, each of the plurality of current-limiting devices…
Resistive memory array using P-I-N diode select device and methods of fabrication thereof
Granted: December 5, 2017
Patent Number:
9837469
An example system includes a processing circuit coupled to a memory system and an interface coupled between the processing circuit and a device. The memory system includes a resistive memory array comprising multiple memory structures. Each memory structure comprises a resistive memory cell and is associated with a P-I-N diode. The processing circuit is to access the resistive memory array responsive to a signal received from the device via the interface.
Memory devices and systems including multi-speed access of memory modules
Granted: December 5, 2017
Patent Number:
9836416
A system, comprising: a plurality of modules, each module comprising a plurality of integrated circuits devices coupled to a module bus and a channel interface that communicates with a memory controller, at least a first module having a portion of its total module address space composed of first type memory cells having a first maximum access speed, and at least a second module having a portion of its total module address space composed of second type memory cells having a second maximum…
Programmable switched capacitor block
Granted: November 28, 2017
Patent Number:
9831864
A first portion of a programmable switched capacitor block includes a first plurality of switched capacitors and a second portion of the programmable switched capacitor block includes a second plurality of switched capacitors. A first switch associated with the first plurality of switched capacitors as well as a second switch associated with the second plurality of switched capacitors may be configured based on a type of analog function that is to be provided. The configuring of the…
Self-aligned trench isolation in integrated circuits
Granted: November 28, 2017
Patent Number:
9831114
A system and method for providing electrical isolation between closely spaced devices in a high density integrated circuit (IC) are disclosed herein. An integrated circuit (IC) comprising a substrate, a first device, a second device, and a trench in the substrate and a method of fabricating the same are also discussed. The trench is self-aligned between the first and second devices and comprises a first filled portion and a second filled portion. The first fined portion of the trench…
Semiconductor device having element separation region formed from a recess-free trench
Granted: November 28, 2017
Patent Number:
9831113
A method of manufacturing a semiconductor device includes forming a silicon nitride film having an opening portion on a semiconductor substrate, forming a silicon oxide film on the silicon nitride film and on a side face of the opening portion, performing an etching treatment to the silicon oxide film so that a sidewall is formed on the side face of the opening portion, forming a trench on the semiconductor substrate with use of the sidewall and the silicon nitride film as a mask, and…
Offset sensor pattern
Granted: November 28, 2017
Patent Number:
9829523
A capacitive sensor array may comprise a plurality of column sensor electrodes and a plurality of row sensor electrodes. The column sensor electrodes may be capacitively coupled with the row sensor electrodes to form a plurality of unit cells each including an intensity center identifying a location of greatest capacitance sensitivity between a row electrode and a column electrode. An axis of a set of row sensor electrodes may cross at least a portion of each row electrode in the set,…
Method of integration of ONO stack formation into thick gate oxide CMOS flow
Granted: November 21, 2017
Patent Number:
9824895
A method of integrating a silicon-oxide-nitride-oxide-silicon (SONOS) transistor into a complementary metal-oxide-silicon (CMOS) baseline process. The method includes the steps of forming the gate oxide layer of at least one metal-oxide-silicon (MOS) transistor prior to forming a non-volatile (NV) gate stack of the SONOS transistor.
Ratio-metric self-capacitance-to-code convertor
Granted: November 14, 2017
Patent Number:
9819360
A circuit, system, and method for converting self capacitance to a digital value may include a pair of charge transfer circuits, each including a deadband switch network, a sensor capacitor or modulation capacitor, and an integration capacitor may be coupled to a comparator to produce a bitstream representative of the capacitance of the sensor capacitor of one of the charge transfer circuits. The bitstream may be used to indicate a capacitance value of the self capacitance through…
Split-gate flash cell formed on recessed substrate
Granted: November 14, 2017
Patent Number:
9818755
A semiconductor device including a non-volatile memory (NVM) cell and method of making the same are disclosed. The semiconductor device includes a metal-gate logic transistor formed on a logic region of a substrate, and the NVM cell integrally formed in a first recess in a memory region of the same substrate, wherein the first recess is recessed relative to a first surface of the substrate in the logic region. Generally, the metal-gate logic transistor further including a planarized…
Systems, methods, and apparatus for memory cells with common source lines
Granted: November 14, 2017
Patent Number:
9818484
Systems, methods, and apparatus are disclosed for implementing memory cells having common source lines. The methods may include receiving a first voltage at a first transistor. The first transistor may be coupled to a second transistor and included in a first memory cell. The methods include receiving a second voltage at a third transistor. The third transistor may be coupled to a fourth transistor and included in a second memory cell. The first and second memory cells may be coupled to…
Hidden markov model processing engine
Granted: November 14, 2017
Patent Number:
9817881
A method, apparatus, and tangible computer readable medium for processing a Hidden Markov Model (HMM) structure are disclosed herein. For example, the method includes receiving Hidden Markov Model (HMM) information from an external system. The method also includes processing back pointer data and first HMM states scores for one or more NULL states in the HMM information. Second HMM state scores are processed for one or more non-NULL states in the HMM information based on at least one…
Device and method for resisting non-invasive attacks
Granted: November 7, 2017
Patent Number:
9813232
A device and method for resisting, non-invasive attacks are disclosed herein. The device includes a random number generator that generates a random number, and a multiplier that multiplies first data and second data in a unit of a bit length determined based on the random number.
Low-power type-C receiver with high idle noise and DC-level rejection
Granted: November 7, 2017
Patent Number:
9811135
Techniques for low-power USB Type-C receivers with high DC-level shift tolerance and high noise rejection are described herein. In an example embodiment, a USB-enabled device comprises a receiver circuit coupled to a Configuration Channel (CC) line of a USB Type-C subsystem. The receiver circuit is configured to receive data from an incoming signal on the CC line even when the incoming signal has more than 250 mV of DC offset with respect to local ground, and to reject the incoming…
Re-enumeration of USB 3.0 compatible devices
Granted: October 31, 2017
Patent Number:
9804859
A host device can download a firmware update to a peripheral device having previously enumerated with the host device. The host device can perform link training with the peripheral device in response to a re-enumeration indication received from the peripheral device. The link training can include switching a Link Training and Status State Machine (LTSSM) in the host device from an active state (U0) to an RX.Detect state and synchronizing with the peripheral device in the RX.Detect state.…
System for re-enumeration of USB 3.0 compatible peripheral devices
Granted: October 31, 2017
Patent Number:
9804858
Described herein is a system comprising a peripheral device that is connected to a host device over a bus compatible with USB 3.0. The host device comprises a reduced functionality USB host controller configured to perform a set of one or more preprogrammed functions from the USB 3.0 specification, and a universal asynchronous receiver and transmitter (UART) configured to sample USB response data received from the peripheral device over the bus.
Integrated circuit to convert no-wire signals to one-wire signals
Granted: October 24, 2017
Patent Number:
9798909
A radio frequency identification (RFID) integrated circuit includes a transceiver and a processing device. The transceiver may to transmit a first continuous wave radio frequency (RF) signal to a bridge in a no-wire format via an antenna, where the transceiver is to start transmitting the modulated or continuous wave RF signal at a first amplitude value and increase an amplitude of the modulated or continuous wave RF signal to a second amplitude value at which an acknowledge (ACK) pulse…
Method of ONO stack formation
Granted: October 17, 2017
Patent Number:
9793284
A method of controlling the thickness of gate oxides in an integrated CMOS process which includes performing a two-step gate oxidation process to concurrently oxidize and therefore consume at least a first portion of the cap layer of the NV gate stack to form a blocking oxide and form a gate oxide of at least one metal-oxide-semiconductor (MOS) transistor in the second region, wherein the gate oxide of the at least one MOS transistor is formed during both a first oxidation step and a…
