Power supply including regulating transistor for providing current to a load and non-volatile memory devices produced accordingly
Granted: February 13, 2018
Patent Number:
9892763
Disclosed are methods, circuits, apparatuses and systems for providing power to a dynamic load such as a non-volatile memory array. According to embodiments, a voltage source may be adapted to generate and output a supply current at substantially a target voltage through a regulating transistor whose channel is in series between an output terminal of said charge pump and an input terminal of said NVM array. A discharge circuit branch coupled to an output terminal of the regulating…
Method and apparatus for data transmission via capacitance sensing device
Granted: February 13, 2018
Patent Number:
9891765
A system made up of a first device which includes a communication interface and a processing device and a second device which includes a touch sensor assembly and a controller, where the controller uses the touch sensor assembly to communicate with the processing device through a capacitor that is jointly formed by the touch sensor assembly and a conductive portion of the communications interface.
Semiconductor device and method of manufacturing the same
Granted: February 6, 2018
Patent Number:
9887178
An example method includes disposing a semiconductor element on a first surface of a substrate. The substrate includes multiple solder balls mounted on a second surface of the substrate that is opposite to the first surface. The semiconductor element includes a bottom surface adjacent to the first surface of the substrate, a top surface, and multiple side surfaces. The example method includes forming a first molding portion to entirely enclose the multiple side surfaces and the top…
Suppression of program disturb with bit line and select gate voltage regulation
Granted: January 30, 2018
Patent Number:
9881683
Techniques for suppression of program disturb in memory devices are described herein. In an example embodiment, a memory device comprises a flash memory array coupled to a control circuit. The flash memory array comprises rows and columns of memory cells, where the memory cells in each row are coupled to a source line and to a select-gate (SG) line, and the memory cells in each column are coupled to a respective bit line (BL). The control circuit is configured to regulate both a first…
Autonomous control in a programmable system
Granted: January 30, 2018
Patent Number:
9880536
A programmable system includes a programmable analog system that is reconfigurable to perform various analog operations, and includes a programmable digital system that is reconfigurable to perform various digital operations. The programmable system also includes a microcontroller capable of reconfiguring and controlling the programmable analog system and the programmable digital system. The programmable digital system is configured to control the programmable analog system autonomously…
Integration of a memory transistor into high-k, metal gate CMOS process flow
Granted: January 23, 2018
Patent Number:
9876020
Memory cells including embedded SONOS based non-volatile memory (NVM) and MOS transistors are described. The memory cell includes a substrate having a non-volatile memory (NVM) region and a plurality of metal-oxide-semiconductor (MOS) regions. A NVM transistor in the NVM region includes a tunnel dielectric on the substrate, a charge-trapping layer on the tunnel dielectric, and a blocking dielectric comprising a high-k dielectric material over the charge-trapping layer. The plurality of…
Phase controller apparatus and methods
Granted: January 16, 2018
Patent Number:
9872346
A phase controller includes a plurality of pulse width modulation (PWM) circuits, a plurality of switching devices, a computing unit, and a latency generator. The plurality of PWM circuits output pulse signals. The plurality of switching devices are coupled to the respective plurality of PWM circuits, and switch on and off based on the pulse signals. The computing unit calculates the pulse signals to be output from the plurality of PWM circuits, based on outputs of the plurality of…
Protecting circuit and integrated circuit
Granted: January 16, 2018
Patent Number:
9871374
A protecting circuit includes: a discharge switch configured to connect to a first terminal and a second terminal; a trigger circuit comprising load devices configured to be connected in series between the first terminal and the second terminal, each of the load devices being configured to consume power; and a shunt circuit comprising, between the trigger circuit and the first terminal or the second terminal, at least one shunt pathway configured to be capable of bypassing at least one…
Automatic scheme to detect multi-standard charger types
Granted: January 9, 2018
Patent Number:
9866055
Techniques are described herein for detecting one of multiple (e.g., at least three) charger types that may be connected to a portable device. In response to detecting a charging device (e.g., a charger) of a particular charger type, the portable device is configured to charge its battery by drawing the maximum voltage and/or current that is/are allowed by the particular charger type. In an example embodiment, a portable device detects a Universal Serial Bus (USB) connection to a…
Biasing circuit for level shifter with isolation
Granted: January 9, 2018
Patent Number:
9866216
A circuit includes a biasing circuit that includes a diode stack coupled to a first node. The biasing circuit can output a biasing signal on the first node. The biasing circuit also includes a transistor, a timer component and a current source. An input of the timer component is coupled to receive an isolation signal. The current source is configured to inject current for a period of time into the diode stack in response to a transition of the ISO signal between a first voltage and a…
Methods to integrate SONOS into CMOS flow
Granted: January 9, 2018
Patent Number:
9865711
A method of forming a transistor is described. In one embodiment the method includes: forming a channel of a transistor in a surface of a substrate; forming a dielectric stack including a first oxide layer overlying the surface of the substrate, a middle layer comprising nitride overlying the first oxide layer and a second oxide layer overlying the middle layer; forming over the dielectric stack a mask exposing source and drain (S/D) regions of the transistor; etching the dielectric…
Capacitive fingerprint sensor with quadrature demodulator and multiphase scanning
Granted: January 9, 2018
Patent Number:
9864894
A fingerprint sensing circuit, system, and method is disclosed. The fingerprint sensor maybe include a plurality of inputs coupled to a plurality of fingerprint sensing electrodes and to an analog front end. The analog front end may be configured to generate at least one digital value in response to a capacitance of at least one of the plurality of fingerprint sensing electrodes. Additionally, the analog front end may include a quadrature demodulation circuit to generate at least one…
Methods and physical computer-readable storage media for initiating re-enumeration of USB 3.0 compatible devices
Granted: January 9, 2018
Patent Number:
9864607
Methods, physical computer-readable media, and devices are provided that allow re-enumeration to be initiated on a USB 3.0-compatible device. The method includes establishing a connection with a host, transmitting an indicator from the device to the host to cause a Link Training and Status State Machine (LTSSM) of the host to move from active state (U0) to one of SS.Inactive and RX.Detect, synchronizing the device with the host, and presenting a new configuration of the device to the…
Input/output multiplexer bus
Granted: January 9, 2018
Patent Number:
9863988
One embodiment includes and I/O bus including a signal line coupled to a signal source and multiple line switches, each line switch to couple a corresponding I/O port to the signal line. Switch logic coupled to the I/O bus may programmatically switch the multiple line switches to couple at least one of the signal source and measurement circuitry to the respective I/O port.
Tool and method for refining a circuit including parametric analog elements
Granted: January 2, 2018
Patent Number:
9858376
A method is provided for designing and implementing a circuit comprising an integrated circuit (IC) including a number of analog and digital circuit elements for which operating parameters can be set. In one embodiment the method includes entering in a circuit design tool embodied in a computer readable medium on a server specified requirements for a circuit, the specified requirements including physical properties to be sensed by the circuit. The circuit is automatically modeled by the…
Integrated circuit including parametric analog elements
Granted: January 2, 2018
Patent Number:
9858367
A parameterizable integrated circuit (IC) and method for designing, refining and implementing a circuit including the parameterizable IC are described. The method begins with receiving information on candidate sensing sub-circuits, parameterizable ICs and user specified requirements for the circuit including physical properties to be sensed and target values for the circuit. Each of the parameterizable ICs include a number of parametric analog and digital circuit elements, and a…
Split-gate flash cell formed on recessed substrate
Granted: December 26, 2017
Patent Number:
9853039
A semiconductor device including a non-volatile memory (NVM) cell and method of making the same are disclosed. The semiconductor device includes a metal-gate logic transistor formed on a logic region of a substrate, and the NVM cell integrally formed in a first recess in a memory region of the same substrate, wherein the first recess is recessed relative to a first surface of the substrate in the logic region. Generally, the metal-gate logic transistor further including a planarized…
Digital driving circuits, methods and systems for display devices
Granted: December 26, 2017
Patent Number:
9852702
A method may include generating display driver signals that vary between only two levels and applying the display driver signals to opposing electrodes of a display segment within a display device. An intrinsic capacitance of the display device filters the display driver signals to generate different analog signal levels at the display segment of the display device. The method varies the pulse density of the display driver signals to select or de-select the display segment based on an…
Voltage adjustment circuit and display device driving circuit
Granted: December 19, 2017
Patent Number:
9846321
A voltage adjustment circuit for adjusting a voltage to be supplied to scanning lines of a display device includes a slope adjustment circuit configured to adjust a slope of a decrease in the voltage based on data that is externally input, and a clamp voltage adjustment circuit configured to adjust a voltage value at which the voltage is clamped based on the data.
RFID interface and interrupt
Granted: December 19, 2017
Patent Number:
9846664
A RFID system includes an RFID controller incorporating a serial bus master coupled via a serial bus to a serial bus slave device, whereby the RFID controller controls power supply and/or power mode of the salve device in order that the slave device is powered and able to communicate with the RFID controller in response to RFID commands received from an RFID reader, and unpowered or in a low power mode otherwise.
