Memory interface configurable for asynchronous and synchronous operation and for accessing storage from any clock
Granted: August 15, 2017
Patent Number:
9734877
A method of operating a memory interface circuit involves selectively operating the memory interface in either a synchronous mode or an asynchronous mode, the synchronous mode controlled by a first clock signal; in asynchronous mode, controlling an address latch for latching an address of a memory location in a memory array, the address latch controlled by an asynchronous address control signal synchronized to a second clock signal that is faster than a third clock signal used to operate…
Pressure detection system for touch-sense devices
Granted: August 15, 2017
Patent Number:
9733745
A touch-sense device includes an overlay, such as a rough overlay or a compliant overlay, on a sensing layer. Use of the overlay changes a response of the sensing layer so that a light press is more distinguishable from a strong press by sensing electronics. Distinguishing the light press from the strong press enables the sensing electronics to report additional information in response to a press. In one example, a sensor signal of the sensing layer attains a first magnitude for a light…
Multiple phase-shift photomask and semiconductor manufacturing method
Granted: August 15, 2017
Patent Number:
9733574
Manufacturing of semiconductor devices often involves performed photolithography to pattern and etch the various features of those devices. Such photolithography involves masking and focusing light onto a surface of the semiconductor device for exposing and etching the features of the semiconductor devices. However, due to design specifications and other causes, the semiconductor devices may not have a perfectly flat light-incident surface. Rather, some areas of the semiconductor device…
Method of depositing copper using physical vapor deposition
Granted: August 8, 2017
Patent Number:
9728414
The present method of forming an electronic structure includes providing a tantalum base layer and depositing a layer of copper on the tantalum layer, the deposition being undertaken by physical vapor deposition with the temperature of the base layer at 50.degree. C. or less, with the deposition taking place at a power level of 300 W or less.
Configurable and power-optimized integrated gate-driver for USB power-delivery and type-C SoCs
Granted: August 8, 2017
Patent Number:
9727123
Techniques for power Field Effect Transistor (power-FET) gate drivers are described herein. In an example embodiment, a device comprises a Universal Serial Bus (USB) subsystem that is disposed in a monolithic integrated circuit (IC). The USB subsystem comprises a gate-driver circuit configured to selectively control an external N-channel power-FET or an external P-channel power-FET.
System and method for controlling a target device
Granted: August 1, 2017
Patent Number:
9720805
Target device monitoring systems and methods are presented. In one embodiment, a host emulation target device control method includes receiving high level express interface direction to change a design element value. The design element values are associated with an operating target device. Design element values corresponding to the direction are created. The design element values are also forwarded to the operating target device in real time.
Integration of a memory transistor into high-k, metal gate CMOS process flow
Granted: August 1, 2017
Patent Number:
9721962
Memory cells including embedded SONOS based non-volatile memory (NVM) and MOS transistors and methods of forming the same are described. Generally, the method includes: forming a gate stack of a NVM transistor in a NVM region of a substrate including the NVM region and a plurality of MOS regions; and depositing a high-k dielectric material over the gate stack of the NVM transistor and the plurality of MOS regions to concurrently form a blocking dielectric comprising the high-k dielectric…
Data writing method and system
Granted: August 1, 2017
Patent Number:
9721665
A data writing method for writing data to a flash memory includes writing an initial value to the data storage area, determining whether or not the writing of the initial value is performed normally based on a write flag, writing data to the data storage area when the writing is performed normally, and erasing a block including the data storage area when the writing is not performed normally. An initial value is written to the data storage area before writing data, so that whether or not…
Reconfigurable circuit having rows of a matrix of registers connected to corresponding ports and a semiconductor integrated circuit
Granted: August 1, 2017
Patent Number:
9720879
A reconfigurable circuit includes a plurality of processing elements and an input/output data interface unit, and the reconfigurable circuit is configured to control connections of the plurality of processing elements for each context. The input/output data interface unit is configured to hold operation input data which is input to the plurality of processing elements and operation output data which is output from the plurality of processing elements. The input/output data interface unit…
Bus sharing scheme
Granted: August 1, 2017
Patent Number:
9720865
A programmable device, having an analog component coupled with an analog bus and a digital component coupled with a digital bus together with a set of 10 pads, each of which capable of being coupled to a bus line of one segment of the analog bus as well as to at least one digital bus line, and where the analog bus is capable of being used to connect a pair of the pads to each other.
Nonvolatile charge trap memory device having a deuterated layer in a multi-layer charge-trapping region
Granted: July 25, 2017
Patent Number:
9716153
Scaling a charge trap memory device and the article made thereby. In one embodiment, the charge trap memory device includes a substrate having a source region, a drain region, and a channel region electrically connecting the source and drain. A tunnel dielectric layer is disposed above the substrate over the channel region, and a multi-layer charge-trapping region disposed on the tunnel dielectric layer. The multi-layer charge-trapping region includes a first deuterated layer disposed on…
Transceiver for communication and method for controlling communication
Granted: July 11, 2017
Patent Number:
9705697
An example embodiment provides a transceiver for communication includes a timing determiner that detects a fall from high level to low level of a bus signal generated by pulse width modulation of a clock signal and input from a communication bus; a transmission data signal delay adjuster that determines a second timing having a predetermined time difference from a first timing, the bus signal rising from the low level to the high level at the first timing; an encoder that extends a low…
High voltage architecture for non-volatile memory
Granted: July 11, 2017
Patent Number:
9704585
A method of erasing, during an erase operation, a non-volatile memory (NVM) cell of a memory device is disclosed. The erasing includes applying a first HV signal (VPOS) to a common source line (CSL). The CSL is shared among NVM cells of a sector of NVM cells. The first HV signal is above a highest voltage of a power supply. The erasing also includes applying the first HV signal to a local bit line (BL).
Fingerprint sensor pattern
Granted: July 11, 2017
Patent Number:
9704012
An example sensor array includes a first electrode disposed in a first layer, multiple second electrodes disposed in a second layer, and multiple third electrodes disposed outside of the first layer. The second electrodes are galvanically isolated from the first electrode and the third electrodes. In a plan view of the fingerprint sensor array, an area of each third electrode is located within an area of the first electrode.
High speed serial peripheral interface memory subsystem
Granted: July 4, 2017
Patent Number:
9697872
A memory subsystem is disclosed. The memory subsystem includes a serial peripheral interface (SPI) double data rate (DDR) volatile memory component, a serial peripheral interface (SPI) double data rate (DDR) non-volatile memory component coupled to the serial peripheral interface (SPI) double data rate (DDR) volatile memory component and a serial peripheral interface (SPI) double data rate (DDR) interface. The serial peripheral interface (SPI) double data rate (DDR) interface accesses…
Integrated circuit including parametric analog elements
Granted: July 4, 2017
Patent Number:
9697312
A design system is provided. In one embodiment the design system includes an input module to receive specification data for a designed circuit including a configurable integrated circuit (IC). The configurable IC includes a number of analog elements for which parameters can be set by the design system, and a plurality of configurable signal path elements including an analog-to-digital converter (ADC) that is utilized in a plurality of different signal paths. The design system further…
Digital-to-analog converter with a sample and hold circuit and a continuous-time programmable block
Granted: June 27, 2017
Patent Number:
9692442
A device, system, and method of a programmable circuit configured to operate in a buffered drive mode and blanking mode is disclosed. The programmable circuit includes a continuous-time digital-to-analog converter (CTDAC), a continuous-time block (CTB), coupled to the CTDAC, and a sample and hold (SH) circuit coupled to the CTDAC and the CTB. The programmable circuit is configured to operate in a buffered drive mode to buffer an output signal from the CTDAC. The programmable circuit, in…
Switching circuit
Granted: June 13, 2017
Patent Number:
9680465
A switching circuit is provided by using an FET with a low gate-source breakdown voltage. The switching circuit includes a PLDMOS with a gate-source breakdown voltage that is lower than a gate-drain breakdown voltage and an impedance converting circuit coupled to the source of the PLDMOS and configured to output substantially the same voltage as an input voltage from the source of the PLDMOS. An input impedance of the converting circuit is higher than an output impedance thereof. The…
Tape chip on lead using paste die attach material
Granted: June 13, 2017
Patent Number:
9679831
According to various embodiments, systems and methods for packaging a semiconductor device are provided. The disclosure discusses a semiconductor die having a top side and a bottom side that is disposed on a lead frame. An adhesive paste is then applied to attach the semiconductor die to the lead frame such that the adhesive paste fixes the die to a portion of the lead frame. The adhesive paste may be applied directly between die and the lead frame or may be applied in conjunction with a…
Integration of a memory transistor into high-k, metal gate CMOS process flow
Granted: June 6, 2017
Patent Number:
9673211
Memory cells including embedded SONOS based non-volatile memory (NVM) and MOS transistors and methods of forming the same are described. Generally, the method includes: forming a gate stack of a NVM transistor in a NVM region of a substrate including the NVM region and a plurality of MOS regions; and depositing a high-k dielectric material over the gate stack of the NVM transistor and the plurality of MOS regions to concurrently form a blocking dielectric comprising the high-k dielectric…
