Buried hard mask for embedded semiconductor device patterning
Granted: June 6, 2017
Patent Number:
9673206
Methods and apparatus for manufacturing semiconductor devices, and such semiconductor devices, are described. According to various aspects of the disclosure, a semiconductor device comprises a first region, a second region, a first polysilicon region, and a second polysilicon region. The first polysilicon region is formed over the first and second regions of the semiconductor device. Portions of the first and polysilicon layers that are uncovered by either of a first mask and a second…
Temperature detection circuit and temperature measurement circuit
Granted: June 6, 2017
Patent Number:
9671293
A temperature detection circuit and a temperature measurement circuit capable of detecting and measuring temperatures precisely are disclosed. The temperature detection circuit includes n temperature detectors (n is an integer of 2 or more), each of the temperature detectors being configured to output a detection signal of high level when a temperature of an object reaches a first value, and a temperature determination part configured to determine whether or not the temperature of the…
Systems and methods for starting up analog circuits
Granted: May 30, 2017
Patent Number:
9667240
Circuits, systems, and methods for starting up analog devices are provided. One circuit includes an output node at an output voltage (VOUT), a comparator configured to be coupled to a reference voltage (VREF), a feedback loop coupling the output node to the comparator, and a turbo circuit coupled between the output and the output node. The turbo circuit is configured to increase VOUT, the comparator is configured to compare VOUT and VREF, and the turbo circuit is enabled and disabled…
Non-volatile memory with silicided bit line contacts
Granted: May 30, 2017
Patent Number:
9666591
An approach to use silicided bit line contacts that do not short to the underlying substrate in memory devices. The approach provides for silicide formation in the bit line contact area, using a process that benefits from being self-aligned to the oxide-nitride-oxide (ONO) nitride edges. A further benefit of the approach is that the bit line contact implant and rapid temperature anneal process can be eliminated. This approach is applicable to embedded flash, integrating high density…
Access methods and circuits for memory devices having multiple banks
Granted: May 30, 2017
Patent Number:
9666255
A method can include storing a plurality of addresses within one cycle of a timing clock, each address corresponding to a storage location of a memory device; and following the one cycle, accessing a plurality of banks of the memory device in response to the stored addresses corresponding to different banks and preventing access to any one of the plurality of banks by more than one address of the one cycle; wherein each bank includes memory cells arranged into rows and columns that…
Single layer sensor pattern
Granted: May 23, 2017
Patent Number:
9658726
A capacitive sensor array comprises large sensor electrodes and small sensor electrodes formed from a single layer of conductive material. Each sensor electrode of a first set of small sensor electrodes is electrically connected to a first pad. A first axis crosses two or more of the sensor electrodes of the first set of small sensor electrodes, and each small sensor electrode of the first set of small sensor electrodes is located on an opposite lateral side of one of the large sensor…
Systems, methods, and devices for bootstrapped power circuits
Granted: May 23, 2017
Patent Number:
9658632
Systems, methods, and devices are disclosed for implementing a bootstrapped power circuit. Devices may include a controller configured to generate an output signal. Devices may include a power converter configured to receive the output signal, configured to store an amount of energy in response to receiving the output signal, and further configured to release the amount of energy in response to detecting a change in the output signal. Devices may include a switch configured to be toggled…
Partially filled contact and trace layout
Granted: May 16, 2017
Patent Number:
9651812
An apparatus including a first layer formed from a first conductive material having a first coefficient of thermal expansion and a second layer, coupled to the first layer, the second layer formed from a second conductive material having a second coefficient of thermal expansion, where the second layer is partially filled.
Systems and methods for downloading code and data into a secure non-volatile memory
Granted: May 16, 2017
Patent Number:
9653004
A method for downloading information into a secure non-volatile memory of a secure embedded device (SED) during a manufacturing or personalization process. The method involves communicating the information and a software program from a device to a temporary storage memory of the SED. The method also involves starting the software program provided to facilitate an initialization of a first key and to facilitate a transfer of at least a portion of the information from the temporary storage…
Low-power touch button sensing system
Granted: May 16, 2017
Patent Number:
9652015
A capacitance sensing circuit receives an application of a power supply. The capacitance sensing circuit controls a switch circuit to connect the power supply to a processing device responsive to the application of the power supply. The capacitance sensing circuit receives, via a control interface and from the processing device, control information to configure the capacitance sensing circuit. The capacitance sensing circuit disconnects the power supply from the processing device…
Ferroelectric random-access memory with pre-patterned oxygen barrier
Granted: May 9, 2017
Patent Number:
9646976
Structure of F-RAM cells are described. The F-RAM cell include a contact extending through a first dielectric layer on a surface of a substrate. A barrier structure is formed over the contact by depositing and patterning a barrier layer. A second dielectric layer is deposited over the patterned barrier layer and planarized to expose a top surface of the barrier structure. A ferro-stack is deposited and patterned over the barrier structure to form a ferroelectric capacitor. A bottom…
10-transistor non-volatile static random-access memory using a single non-volatile memory element and method of operation thereof
Granted: May 9, 2017
Patent Number:
9646694
A memory including an array of nvSRAM cells and method of operating the same are provided. Each nvSRAM cell includes a volatile charge storage circuit, and a non-volatile charge storage circuit including exactly one non-volatile memory (NVM) element, a first transistor coupled to the NVM element through which data true is coupled to the volatile charge storage circuit, a second transistor coupled to the NVM element through which a complement of the data is coupled to the volatile charge…
Memory device with internal combination logic
Granted: May 9, 2017
Patent Number:
9646661
Embodiments of the present invention include an apparatus, method, and system for integrating data processing logic with memory. An embodiment of a memory integrated circuit is designed to execute a task on the data in a memory array within a memory integrated circuit. The memory integrated circuit can include a memory array, a data access component, a data holding component, and a logic component. The data access component can be coupled to the memory array and configured to provide an…
Access methods and circuits for memory devices having multiple channels and multiple banks
Granted: May 2, 2017
Patent Number:
9640237
An integrated circuit (IC) device can include a plurality of banks, each including a plurality of memory cells, and separately accessible according to a received bank address value, each bank configured to enable accesses on different phases of an internal clock signal; and a plurality of channel groups, each channel group including a plurality of channels, each channel including its own data connections, address connections, and control input connections for accessing the banks, the…
Fingerprint sensor-compatible overlay material
Granted: May 2, 2017
Patent Number:
9639734
A fingerprint sensor-compatible overlay material which uses anisotropic conductive material to enable accurate imaging of a fingerprint through an overlay is disclosed. The anisotropic conductive material has increased conductivity in a direction orthogonal to the fingerprint sensor, increasing the capacitive coupling of the fingerprint to the sensor surface, allowing the fingerprint sensor to accurately image the fingerprint through the overlay. Methods for forming a fingerprint…
Methods and sensors for multiphase scanning in the fingerprint and touch applications
Granted: May 2, 2017
Patent Number:
9639733
Techniques for fully-differential multi-phase scanning in capacitive fingerprint applications are described herein. In an example embodiment, a system comprises a capacitive fingerprint sensor array and a processing device coupled to the capacitive fingerprint sensor array. The processing device is configured at least to: scan the capacitive fingerprint sensor array in a fully-differential multi-phase mode; receive a plurality of measurements that represents a portion of finger on the…
Differential sigma-delta capacitance sensing devices and methods
Granted: May 2, 2017
Patent Number:
9639226
A capacitance sensing device can include a reference circuit configured to connect to a reference capacitance, and to generate an electrical reference signal that varies over time according to the reference capacitance and a compare signal; a sense circuit configured to connect to a sense capacitance, and to generate an electrical sense signal that varies over time according to a sense capacitance; a compare circuit having compare inputs coupled to receive the sense signal and the…
Integrated circuit device with programmable analog subsystem
Granted: April 25, 2017
Patent Number:
9634667
An integrated circuit (IC) device can include a plurality of analog blocks, including at least one fixed function analog circuit, and at least one reconfigurable analog circuit block selected from: a continuous time (CT) block comprising a plurality of reconfigurable amplifier circuits and a discrete time block comprising amplifiers with a reconfigurable switch network; an analog multiplexer (MUX) configured to selectively connect any of a plurality of input/outputs (I/Os) of the IC…
Methods, circuits, devices, systems and machine executable code for reading from a non-volatile memory array
Granted: April 25, 2017
Patent Number:
9632867
Disclosed is a method for reading from a non-volatile memory (NVM) device including: retrieving a set of data from an NVM array according to a read sequence for a requested set of logical memory locations received from a host device, detecting errors in the set of data, preparing an error indicator to be output to a host device substantially upon detection of the errors and outputting the error indication in response to a command being received from the host device.
Ball grid structure
Granted: April 18, 2017
Patent Number:
9627306
An apparatus includes a contact grid array disposed on a substrate in a non-orthogonal row-column format with connection elements arranged in a hexagonal configuration. The contact grid array has an orientation based, at least in part, on an area available for the contact grid array on the substrate. A method to determine the orientation of the contact grid array includes identifying the area available for a contact grid array on a substrate and determining the orientation for the…
