Low-power implementation of Type-C connector subsystem
Granted: July 26, 2016
Patent Number:
9400546
Techniques for low-power implementation of a Universal Serial Bus (USB) Type-C connector subsystem are described herein. In an example embodiment, an integrated circuit (IC) chip device comprises a Universal Serial Bus (USB) Type-C subsystem. The Type-C subsystem is configured to operate an Ra termination circuit that consumes no more than 100 ?A of current after the Ra termination circuit is applied to a Vconn line of the Type-C subsystem, and/or to operate one or more standby reference…
Capacitive field sensor with sigma-delta modulator
Granted: July 26, 2016
Patent Number:
9400298
A capacitive sensor includes a switching capacitor circuit, a comparator, and a charge dissipation circuit. The switching capacitor circuit reciprocally couples a sensing capacitor in series with a modulation capacitor during a first switching phase and discharges the sensing capacitor during a second switching phase. The comparator is coupled to compare a voltage potential on the modulation capacitor to a reference and to generate a modulation signal in response. The charge dissipation…
Semiconductor device and method for manufacturing thereof
Granted: July 19, 2016
Patent Number:
9397025
The present invention provides a semiconductor device including: a semiconductor chip; a lead frame provided with a recessed portion on at least one of an upper surface or a lower surface thereof, and electrically coupled to the semiconductor chip; and a resin section that molds the semiconductor chip and the lead frame, and is provided with an opening above the recessed portion. By inserting a conductive pin (not shown) into the recessed portion through the opening, a plurality of…
Semiconductor device with stop layers and fabrication method using ceria slurry
Granted: July 19, 2016
Patent Number:
9396959
The present invention provides a method of fabricating a semiconductor device including forming stop layers (32) that include silicon oxy-nitride films above a semiconductor substrate, forming a cover film (34) between and on the stop layers, in which a top surface of the cover film above a region between the stop layers is higher than top surfaces of the stop layers, and polishing the cover film to the stop layers by using ceria slurry, and also provides a semiconductor device including…
Control apparatus, switching power supply and control method for maintaining power conversion efficiency
Granted: July 12, 2016
Patent Number:
9391512
Disclosed herein are control apparatus, switching power supply, and control method embodiments for maintaining power conversion efficiency. An embodiment operates by determining whether or not a current of an inductor of the switching power supply has become less than or equal to a predetermined value, controlling a reference voltage based on at least one of a result of the determining or a result of comparing a voltage according to an output voltage of the switching power supply and the…
Memory devices and systems including cache devices for memory modules
Granted: July 12, 2016
Patent Number:
9390783
A memory apparatus may include one or more cache memory integrated circuit (ICs), each of which may have compare circuitry that compares a received address with stored compare values, a cache memory that provides cached data in response to the compare circuitry, a controller interface having at least address and control signal input terminals, and a module output connection having at least address and control signal output terminals corresponding to the address and control signal input…
Flip-chip package covered with tape
Granted: July 5, 2016
Patent Number:
9385014
A manufacturing method of a semiconductor device includes arranging a melted resin on a substrate, arranging a semiconductor chip on the melted resin, pressing the semiconductor chip and flip-chip mounting the semiconductor chip on the substrate, and hardening the melted resin with the melted resin being subjected to a fluid pressure and forming a resin portion.
Endurance of silicon-oxide-nitride-oxide-silicon (SONOS) memory cells
Granted: June 28, 2016
Patent Number:
9378821
Apparatuses and methods of pulse shaping a pulse signal for programming and erasing a Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) memory cell are described. In one method a pulse shape of a pulse signal is controlled to include four or more phases for programming or erasing a SONOS memory cell. A write cycle is performed to program or erase the SONOS memory with the pulse signal with the four or more phases.
Remote control system
Granted: June 28, 2016
Patent Number:
9380248
An example system includes a remote control and a host device. The remote control is configured to communication through a first communication interface and a second communication interface. The host device is configured to retrieve command information from a remote computer through a third communication interface, and responsive to one or more requests from the remote control, to transfer the command information to the remote control through the first communication interface, the remote…
Non-volatile memory device with an EPLI comparator
Granted: June 28, 2016
Patent Number:
9378829
A non-volatile memory device comprising a memory cell array including memory cells distributed among a plurality of sectors; a controller operable to program, read, and erase memory cells in said memory array, said controller further operable to generate and store EPLI values for programming a number of EPLI bits in one of said plurality of sectors with said stored EPLI values; and a comparator to compare said stored EPLI values with EPLI values programmed in said EPLI bits.
Inter-bus communication interface device
Granted: June 28, 2016
Patent Number:
9378165
There is provided an inter-bus communication interface device capable of efficiently performing transfer of data between a plurality of devices connected to different buses, respectively. When communication data is transmitted, a first device writes the communication data into a buffer, whereas when communication control information is transmitted, the first device writes the communication control information into a register. A control circuit passes the communication data stored in the…
Analog circuit cell array having some transistors that include two connected gate electrodes and two connected source regions
Granted: June 21, 2016
Patent Number:
9373621
An analog circuit cell array includes a plurality of transistor cell arranged in an array. Each of the transistor cells includes a first source region, a first channel region, a common drain region, a second channel region, and a second source region arranged in sequence one adjacent to another; and a first gate electrode and a second gate electrode formed on the first channel region and the second channel region, respectively, and wherein the first gate electrode and the second gate…
Non-volatile FINFET memory array and manufacturing method thereof
Granted: June 21, 2016
Patent Number:
9373514
An electronic device includes a substrate with a semiconducting surface having a plurality of fin-type projections coextending in a first direction through a memory cell region and select gate regions. The electronic device further includes a dielectric isolation material disposed in spaces between the projections. In the electronic device, the dielectric isolation material in the memory cell regions have a height less than a height of the projections in the memory cell regions, and the…
Auto resume of irregular erase stoppage of a memory sector
Granted: June 21, 2016
Patent Number:
9373405
Disclosed herein are system, method and/or computer program product embodiments for automatically resuming an irregular erasure stoppage in a sector of a memory system. An embodiment includes storing information related to any completed sub-stage of a multi stage erasure process and the corresponding memory sector address in a dedicated memory. After an irregular erasure stoppage occurs, an embodiment reads the information from the dedicated memory and resumes the erasure process of the…
Generation of wake-up words
Granted: June 21, 2016
Patent Number:
9373321
A method, system and tangible computer readable medium for generating one or more wake-up words are provided. For example, the method can include receiving a text representation of the one or more wake-up words. A strength of the text representation of the one or more wake-up words can be determined based on one or more static measures. The method can also include receiving an audio representation of the one or more wake-up words. A strength of the audio representation of the one or more…
System and method of visualizing capacitance sensing system operation
Granted: June 14, 2016
Patent Number:
9367166
Systems and methods of visualizing capacitance sensing system operation. A graphical user interface for visualizing capacitance sensing system operation includes a first window. The window includes a representation of a physical layout of a plurality of sensor devices on a target apparatus. The graphical user interface is operable to accept input from a pointing device to select a selected sensor from the plurality of sensor devices. A second window is for displaying capacitive sensing…
Memory first process flow and device
Granted: June 14, 2016
Patent Number:
9368606
Semiconductor devices and methods of manufacturing such devices are described herein. According to embodiments, a semiconductor device includes a memory gate disposed in a first region of the semiconductor device. The memory gate may include a first gate conductor layer disposed over a charge trapping dielectric. A select gate may be disposed in the first region of the semiconductor device adjacent to a sidewall of the memory gate. A sidewall dielectric may be disposed between the…
Integrated circuits with non-volatile memory and methods for manufacture
Granted: June 14, 2016
Patent Number:
9368588
Semiconductor devices and the manufacture of such semiconductor devices are described. According to various aspects of the disclosure, a semiconductor device can include a memory region, a first logic region, and a second logic region. A select gate can be formed in the memory region of the device and a first logic gate formed in the logic region. A charge trapping dielectric can then be disposed and removed from a second logic region. A gate conductor layer can then be disposed on the…
Method of fabricating a semiconductor device used in a stacked-type semiconductor device
Granted: June 14, 2016
Patent Number:
9368424
A method of fabricating a semiconductor device includes the steps of providing a heat-resistant sheet on an interposer so as to cover electrode terminals provided on the interposer, and sealing a semiconductor chip on the interposer sandwiched between molds with a sealing material. The electrode terminals are covered by the heat-resistant resin for protection, and the semiconductor chip is then sealed with resin. It is thus possible to avoid the problem in which contaminations adhere to…
Line-edge roughness improvement for small pitches
Granted: June 14, 2016
Patent Number:
9368393
A method for mitigating line-edge roughness on a semiconductor device. The method includes line-edge roughness mitigation techniques in accordance with embodiments of the present invention. The techniques include: reducing the SiON film thickness below a conventional thickness; increasing the photoresist thickness above a conventional thickness; etching the SiON film with an etch bias power less than a conventional wattage amount with an overetch percentage less than a conventional…
