System and method of visualizing capacitance sensing system operation
Granted: June 14, 2016
Patent Number:
9367166
Systems and methods of visualizing capacitance sensing system operation. A graphical user interface for visualizing capacitance sensing system operation includes a first window. The window includes a representation of a physical layout of a plurality of sensor devices on a target apparatus. The graphical user interface is operable to accept input from a pointing device to select a selected sensor from the plurality of sensor devices. A second window is for displaying capacitive sensing…
CT-NOR differential bitline sensing architecture
Granted: June 7, 2016
Patent Number:
9362293
Providing for a non-volatile semiconductor memory architecture that achieves high read performance is described herein. In one aspect, an array of memory transistors arranged electrically in serial is configured to control a gate voltage of a pass transistor. The pass transistor, in turn, enables current flow between two metal bitlines of the semiconductor memory architecture. Accordingly, a relative voltage or relative current of the two metal bitlines can be measured and utilized to…
Semiconductor device and method for manufacturing the same
Granted: June 7, 2016
Patent Number:
9362287
A semiconductor device includes: a first transistor and a second transistor disposed in or on a silicon substrate; an element isolation structure that isolates the first transistor and the second transistor, the element isolation structure comprising at least one of a first element isolation film disposed in a region of a first well disposed in a formation area of the first transistor, or a second element isolation film disposed in a region of a second well disposed in a formation area…
Method of increasing read current window in non-volatile memory
Granted: June 7, 2016
Patent Number:
9361994
A memory structure is provided including an array of non-volatile memory (NVM) cells arranged in rows and columns, each cell including a NVM transistor having a body bias terminal coupled to body bias supply. The memory structure further includes a control system to control the body bias supply to adjust a body bias voltage coupled to the body bias terminals during read operations of the memory structure to compensate for shifts in threshold voltages (VTH) of the NVM transistors to…
Multi-channel, multi-bank memory with wide data input/output
Granted: June 7, 2016
Patent Number:
9361973
An integrated circuit (IC) can include M memory banks, where M is greater than 2, and each memory bank is separately accessible according to a received address value; N channels, where N is greater than 2, and each channel includes its own a data connections, address connections, and control input connections for executing a read or write access to one of the memory banks in synchronism with a clock signal; and a controller subsystem configured to control accesses between the channels…
Touch sensor conductor routing
Granted: June 7, 2016
Patent Number:
9360972
An example apparatus includes a sensing area including a sensor matrix, a first conductor and a second conductor. The first conductor is coupled to a first sensor of the sensor matrix and is configured to be coupled to a sensing module. The second conductor is coupled to a second sensor of the sensor matrix and is configured to be coupled to the sensing module. In embodiments, the first sensor consumes a first area, the second sensor and a length of the first conductor reside within a…
Cursor control device and method of operation
Granted: June 7, 2016
Patent Number:
9360968
We describe an apparatus including a plurality of sensing elements, a conductive layer, and a compressive layer interposed between the plurality of sensing elements and the conductive layer. The conductive layer can include a plurality of segments. A user applies a force to an actuator positioned over the conductive layer. The actuator changes a capacitance of at least one capacitor formed by at least one of the plurality of sensing elements, the conductive layer (at least one segment),…
Non-volatile memory and method of operating the same
Granted: May 31, 2016
Patent Number:
9355725
A memory structure including a memory array of a plurality of memory cells arranged in rows and columns, the plurality of memory cells including a pair of adjacent memory cells in a row of the memory array, wherein the pair of adjacent memory cells include a single, shared source-line through which each of the memory cells in the pair of adjacent memory cells is coupled to a voltage source. Methods of operating a memory including the memory structure are also described.
Embedded SONOS based memory cells
Granted: May 31, 2016
Patent Number:
9356035
A memory device that includes a non-volatile memory (NVM) transistor which has an indium doped channel and a gate stack overlying the channel formed in a first region of a substrate and a metal-oxide-semiconductor (MOS) transistor formed in a second region of the substrate in which the gate oxide of the MOS and the oxide layer of the NVM transistor are formed concurrently.
Oxide-nitride-oxide stack having multiple oxynitride layers
Granted: May 31, 2016
Patent Number:
9355849
A semiconductor device including an oxide-nitride-oxide (ONO) structure having a multi-layer charge storing layer and methods of forming the same are provided. Generally, the method involves: (i) forming a first oxide layer of the ONO structure; (ii) forming a multi-layer charge storing layer comprising nitride on a surface of the first oxide layer; and (iii) forming a second oxide layer of the ONO structure on a surface of the multi-layer charge storing layer. Preferably, the charge…
Apparatus, method, and manufacture for using a read preamble to optimize data capture
Granted: May 31, 2016
Patent Number:
9355051
A memory controller is provided. In response to a burst read command that includes a target address, the memory controller provides, to one or more busses, data stored in memory at the target address after dummy clock cycles have occurred. The memory controller also provides a preamble on the bus(ses) during some of the dummy clock cycles. The preamble includes a data training pattern.
Automated loading/unloading of devices for burn-in testing
Granted: May 31, 2016
Patent Number:
9354272
The automatic loading and unloading of devices for burn-in testing is facilitated by loading burn-in boards in a magazine with the stacked boards in the magazine moved into and out of a burn-in oven by means of a trolley. The trolley can include an elevator whereby a plurality of magazines can be stacked in the oven for the simultaneous burn-in testing of devices mounted on the burn-in boards. Each board has rollers on one end which are engagable by pneumatically actuated cam mechanisms…
Nitridation oxidation of tunneling layer for improved SONOS speed and retention
Granted: May 24, 2016
Patent Number:
9349877
A nonvolatile trapped-charge memory device and method of fabricating the same are described. Generally, the memory device includes a tunneling layer on a substrate, a charge trapping layer on the tunneling layer, and a blocking layer on the charge trapping layer. The tunneling layer includes a nitrided oxide film formed by annealling an oxide grown on the substrate using a nitrogen source. The tunneling layer comprises a first region proximate to the substrate, and a second region…
Oxide-nitride-oxide stack having multiple oxynitride layers
Granted: May 24, 2016
Patent Number:
9349824
A method of fabricating a memory device is described. Generally, the method includes: forming a tunneling layer on a substrate; forming on the tunneling layer a multi-layer charge storing layer including at least a first charge storing layer comprising an oxygen-rich oxynitride overlying the tunneling layer, and a second charge storing layer overlying the first charge storing layer comprising a silicon-rich and nitrogen-rich oxynitride layer that is oxygen-lean relative to the first…
Damascene metal-insulator-metal (MIM) device with improved scaleability
Granted: May 17, 2016
Patent Number:
9343666
A present method of fabricating a memory device includes the steps of providing a dielectric layer, providing an opening in the dielectric layer, providing a first conductive body in the opening, providing a switching body in the opening, the first conductive body and switching body filling the opening, and providing a second conductive body over the switching body. In an alternate embodiment, a second dielectric layer is provided over the first-mentioned dielectric layer, and the…
Integration of semiconductor memory cells and logic cells
Granted: May 17, 2016
Patent Number:
9343470
A polysilicon gate electrode is formed in a memory cell area, and a dummy polysilicon gate electrode is formed in a logic cell area of a silicon substrate. The dummy polysilicon gate electrode is removed and a gate insulation film and a metal gate electrode having a recess portion are formed. Further, contact holes are formed on source regions and drain regions of the memory cell area and the logic cell area. The recess portion of the metal gate electrode and the contact holes are filled…
Simultaneous programming of many bits in flash memory
Granted: May 10, 2016
Patent Number:
9336890
A semiconductor device includes: a plurality of memory cells; a plurality of local bit lines connected to respective memory cells of the plurality of memory cells; and a first amplifier. The first amplifier receives read data from each local bit line of the plurality of local bit lines and determines a transition speed of an output level of the first amplifier in response to receiving a combination of at least two pieces of read data. The first amplifier transfers, based on the…
Electroplating apparatus and method with uniformity improvement
Granted: May 10, 2016
Patent Number:
9334578
An electroplating system is provided. The electroplating system includes a divided electrode that is arranged to simultaneously provide a plurality of line currents for an electroplating process. The system includes a current control component that is coupled to the divided electrode. The current control component is configured to determine the magnitude of each of the line currents. The current control component is also configured to regulate individual line currents based, at least in…
Authenticating ferroelectric random access memory (F-RAM) device and method
Granted: May 3, 2016
Patent Number:
9330251
A memory device including a ferroelectric memory array is described. In one embodiment, the ferroelectric memory array includes a user memory space. The memory device includes control logic configured to provide external read and write access for a host system to the user memory space upon authentication between the host system and the memory device. The host system accesses the user memory space and communicates with the control logic through address, data and control buses. The memory…
Semiconductor device and method for fabricating thereof
Granted: May 3, 2016
Patent Number:
9331180
A silicon nitride film, which is a second hard mask, is dry etched to be removed completely. The silicon nitride film, which is formed on a sidewall of a silicon nitride film used as a first hard mask, has a relatively low etching rate. Therefore, if the silicon nitride film is continued etching until the corresponding portion thereof is removed, polysilicon is etched in a direction of depth in trench shape. Then, floating gates in adjacent cells are separated and a step portion of the…
