System level interconnect with programmable switching
Granted: April 26, 2016
Patent Number:
9325320
A plurality of functional elements are all located on a same integrated circuit wherein at least one of the functional elements comprises a micro-controller. A configuration data store in the integrated circuit stores configuration values loaded by the micro-controller. A plurality of connectors are configured to connect the integrated circuit to external signals. A programmable interconnect also located in the integrated circuit programmably connects together the plurality of functional…
Power supply device, control circuit, electronic device and control method for power supply
Granted: April 26, 2016
Patent Number:
9325239
A power supply device that includes a switch circuit to which an input voltage is supplied, a coil coupled between the switch circuit and an output terminal from which an output voltage is outputted. A voltage adding circuit adds a slope voltage to a reference voltage. A control unit compares a feedback voltage corresponding to the output voltage and the reference voltage and switches the switch circuit at a timing corresponding to a comparison result of the feedback voltage and the…
Method and apparatus for sensing movement of a human interface device
Granted: April 19, 2016
Patent Number:
9317138
A system includes circuitry to exchange multiple radio signals with a peripheral device. The system further includes a processing device configured to identify time periods for the multiple radio signals to travel between the circuitry and the peripheral device, wherein the processing device is configured to determine a distance and direction of movement of the peripheral device according to the identified time periods.
Signal processor and communication device
Granted: April 19, 2016
Patent Number:
9319162
A signal processor includes a period detection section which detects that a period is currently used for communication of a frame; a pattern detection section which detects, from the received signal, a first signal pattern by which the end of communication of the frame is recognized; and an output processing section which outputs the received signal to a controller; configured to instruct, upon detection of the first signal pattern in the period being currently used for communication of…
Method for fabricating a damascene self-aligned ferroelectric random access memory (F-RAM) having a ferroelectric capacitor aligned with a three dimensional transistor structure
Granted: April 19, 2016
Patent Number:
9318693
A method for a non-volatile, ferroelectric random access memory (F-RAM) device that includes a ferroelectric capacitor aligned with a preexisting structure is described. In one embodiment, the method includes forming an opening in an insulating layer over a contact in a planar surface of a substrate to expose at least a portion of the contact. Next a self-aligned contact (SAC) is formed electrically coupling to the contact, the SAC medially located in the opening and proximal to a…
Buried hard mask for embedded semiconductor device patterning
Granted: April 19, 2016
Patent Number:
9318498
Methods and apparatus for manufacturing semiconductor devices, and such semiconductor devices, are described. According to various aspects of the disclosure, a semiconductor device can be manufactured by forming a core region of the semiconductor device and forming a periphery region of the semiconductor device. A first polysilicon region can then be formed over the core and periphery regions of the semiconductor device. A first mask is formed on the first poly silicon layer and a second…
Method and apparatus for protection against process-induced charging
Granted: April 19, 2016
Patent Number:
9318373
A semiconductor device (400) for improved charge dissipation protection includes a substrate (426), a layer of semiconductive or conductive material (406), one or more thin film devices (408) and a charge passage device (414). The thin film devices (408) are connected to the semiconductive or conductive layer (406) and the charge passage device (414) is coupled to the thin film devices (408) and to the substrate (426) and provides a connection from the thin film devices (408) to the…
Dielectric extension to mitigate short channel effects
Granted: April 19, 2016
Patent Number:
9318333
In patterning a transistor, some of a layer of gate dielectric material is allowed to remain over a semiconductor substrate upon which the transistor is formed. This remaining dielectric material retards the implantation of dopants into the underlying substrate, effectively lengthening a channel region of the transistor. This mitigates unwanted short channel effects, such as leakage currents, for example, and thus mitigates yield loss by establishing a transistor that performs in a more…
Multiplexing auxiliary processing element and semiconductor integrated circuit
Granted: April 19, 2016
Patent Number:
9317475
A multiplexing auxiliary processing element (PE) performs a process that includes the operations of receiving signals of a plurality of upstream processing elements (PEs) including a plurality of pairs of PEs arranged on the input side; supplying the signals from the upstream PEs to a multiplex PE that is multiplexed and used so that the signals are subjected to a predetermined process by the multiplex PE; receiving the processed signals subjected to the predetermined process by the…
Rapid memory buffer write storage system and method
Granted: April 19, 2016
Patent Number:
9317445
Efficient and convenient storage systems and methods are presented. In one embodiment a storage system includes a host for processing information, a memory controller and a memory. The memory controller controls communication of the information between the host and the memory, wherein the memory controller routes data rapidly to a buffer of the memory without buffering in the memory controller. The memory stores the information. The memory includes a buffer for temporarily storing the…
Method of manufacturing a semiconductor device having a chip mounted on an interposer
Granted: April 12, 2016
Patent Number:
9312252
A semiconductor device 100 includes: a first semiconductor package 10; a first interposer 12 having an upper surface on which the first semiconductor package 10 is mounted; a first molding resin 14 that is provided on the upper surface of the first interposer 12 and seals the first semiconductor package 10; a second semiconductor package 20 mounted on an upper surface of the first molding resin 14; a second interposer 22 on which the second semiconductor package 20 is mounted by flip…
Full-wave synchronous rectification for self-capacitance sensing
Granted: April 12, 2016
Patent Number:
9310953
An apparatus and method to measure a self-capacitance of a capacitive sense array is described. The apparatus includes a first integrating capacitor, a first modulator, a second integrating capacitor, and a second modulator. The first modulator is operatively coupled to the first integrating capacitor. The second modulator is operatively coupled to the second integrating capacitor. The first modulator in conjunction with the first integrating capacitor and the second modulator in…
Memory transistor with multiple charge storing layers and a high work function gate electrode
Granted: April 5, 2016
Patent Number:
9306025
A semiconductor device includes an oxide-nitride-oxide (ONO) dielectric stack on a surface of a substrate, and a high work function gate electrode formed over a surface of the ONO dielectric stack. The ONO dielectric stack includes a multi-layer charge storage layer including a silicon-rich, oxygen-lean top silicon nitride layer and an oxygen-rich bottom silicon nitride layer. The high work function gate electrode includes a P+ doped polysilicon layer.
Methods of fabricating an F-RAM
Granted: April 5, 2016
Patent Number:
9305995
Methods of forming F-RAM cells are described. The method includes forming a contact extending through a first dielectric layer on a surface of a substrate. A barrier structure is formed over the contact by depositing and patterning a barrier layer. A second dielectric layer is deposited over the patterned barrier layer and planarized to expose a top surface of the barrier structure. A ferro-stack is deposited and patterned over the barrier structure to form a ferroelectric capacitor. A…
Memory device with internal combination logic
Granted: April 5, 2016
Patent Number:
9305614
Embodiments of the present invention include an apparatus, method, and system for integrating data processing logic with memory. An embodiment of a memory integrated circuit is designed to execute a task on the data in a memory array within a memory integrated circuit. The memory integrated circuit can include a memory array, a data access component, a data holding component, and a logic component. The data access component can be coupled to the memory array and configured to provide an…
Memory controller devices, systems and methods for translating memory requests between first and second formats for high reliability memory devices
Granted: April 5, 2016
Patent Number:
9304953
A device can include an interface circuit configured to translate memory access requests at a controller interface of the interface circuit into signals at a memory device interface of the interface circuit that is different from the controller interface, the interface circuit including a write buffer memory configured to store a predetermined number of data values received at a write input of the controller interface, and a read buffer memory configured to mirror a predetermined number…
Watchdog timer with mode dependent time out
Granted: March 29, 2016
Patent Number:
9298531
A method and apparatus to operate a watchdog timer having a first time out period in a processing system. The watchdog timer receives an indication of a change in a mode of operation in the processing system. In response to the change in the mode of operation of the processing system, the watchdog timer changes the time out period to a second time out period corresponding to the new mode of operation.
Ruthenium interconnect with high aspect ratio and method of fabrication thereof
Granted: March 29, 2016
Patent Number:
9299643
An electrically conductive interconnect is provided through an opening in a dielectric layer, electrically connecting two conductive layers. In one embodiment, the interconnect is formed by ruthenium entirely filling the opening in the dielectric layer. In another embodiment, an adhesion layer of titanium is provided in the opening prior to providing the ruthenium. In using this approach, an aspect ratio (i.e., the ratio of the length of the interconnect to the width thereof) of 20:1 or…
Transistor formation method using sidewall masks
Granted: March 29, 2016
Patent Number:
9299578
There is provided a method of fabricating a semiconductor device including forming a first film on a base layer, forming a first mask pattern on the first film, the first mask pattern having mask portions arranged at a given pitch, forming first sidewall films on sidewalls of the first mask pattern by etchback of a deposited second film, removing the first mask pattern, and forming a second mask pattern composed of the first sidewall films and second sidewall films defined by etchback of…
SONOS ONO stack scaling
Granted: March 29, 2016
Patent Number:
9299568
A method of scaling a nonvolatile trapped-charge memory device and the device made thereby is provided. In an embodiment, the method includes forming a channel region including polysilicon electrically connecting a source region and a drain region in a substrate. A tunneling layer is formed on the substrate over the channel region by oxidizing the substrate to form an oxide film and nitridizing the oxide film. A multi-layer charge trapping layer including an oxygen-rich first layer and…
