Pipelining in a memory
Granted: September 22, 2015
Patent Number:
9142270
A system including a memory cell array including a plurality of memory cells, and a writing device to generate multiple back-to-back write pulses to write to target memory cells from among the plurality of memory cells, the multiple back-to-back write pulses overlapping during an overlap duration, the overlap duration being adjustable based on a performance parameter of the memory cell array.
Power-efficient voice activation
Granted: September 22, 2015
Patent Number:
9142215
A voice activation system is provided. The voice activation system includes a first stage configured to output a first activation signal if at least one energy characteristic of a received audio signal satisfies at least one threshold and a second stage configured to transition from a first state to a second state in response to the first activation signal and, when in the second state, to output a second activation signal if at least a portion of a profile of the audio signal…
Data pattern analysis
Granted: September 22, 2015
Patent Number:
9142209
A method and apparatus receive multiple data pattern analysis requests from a controller and substantially simultaneously perform, with multiple data pattern analysis units, multiple data pattern analyses on one or more portions of a data stream.
Dynamically switching communication modes in multi-standard wireless communication devices
Granted: September 15, 2015
Patent Number:
9137849
A method may include selecting at least an initial communication mode from a plurality of communication modes that each communicate with a master device using time division multiple access (TDMA); and dynamically switching communication modes between the master device and at least slave device in accordance with at least one predetermined characteristic of the wireless system.
Real-time data pattern analysis system and method of operation thereof
Granted: September 15, 2015
Patent Number:
9135918
A method of operation of a real-time data-pattern analysis system includes: providing a memory module, a computational unit, and an integrated data transfer module arranged within an integrated circuit die; storing a data pattern within the memory module; transferring the data pattern from the memory module to the computational unit using the integrated data transfer module; and comparing processed data to the data pattern using the computational unit.
Systems and methods for providing high voltage to memory devices
Granted: September 8, 2015
Patent Number:
9129686
Apparatus, systems, and methods for providing high voltage to memory devices are provided. One apparatus includes a low voltage input and a two-rail level shifting. The two-rail level shifting is configured to increase the low voltage or to decrease the low voltage to an amount that is less than or equal to a ground potential based on the amount of the low voltage. A system includes a low voltage input for receiving a voltage and a two-rail level shifting coupled to the low voltage…
Line plotting method
Granted: September 8, 2015
Patent Number:
9129437
A line plotting method for plotting lines whose coordinates are given on a display screen on which pixels are arranged according to a prescribed rule, the method includes correcting coordinates at the end point of a line on the basis of which the end point is a starting point or an ending point or whether the end point is inside a prescribed frame determining whether a direction from a starting point of a line after correction toward its ending point horizontally or vertically is the…
Noise filtering devices, systems and methods for capacitance sensing devices
Granted: September 8, 2015
Patent Number:
9128570
A capacitance sensing system can filter noise that presents in a subset of electrodes in the proximity of a sense object (i.e., finger). A capacitance sensing system can include a sense network comprising a plurality of electrodes for generating sense values; a noise listening circuit configured to detect noise on a plurality of the electrodes; and a filtering circuit that enables a filtering for localized noise events when detected noise values are above one level, and disables the…
Load driver
Granted: September 1, 2015
Patent Number:
9124264
A method of driving an output terminal to a voltage, in which an input signal is received, an appropriate output voltage and output voltage range are determined based on the input signal, an output driver is configured to a first mode and the output driver drives the output terminal to a voltage within the voltage range, the output driver is configured to a second mode and the output driver drives the output terminal to a voltage approximately equal to the appropriate output voltage.
On-chip calibration method
Granted: September 1, 2015
Patent Number:
9124285
A system for the calibration of a programmable system-on-a-chip is described. More specifically, embodiments of the present invention relate to a system that calibrates a programmable analog block in a system-on-a-chip without the use of external components.
Method of forming drain extended MOS transistors for high voltage circuits
Granted: September 1, 2015
Patent Number:
9123642
A device including both drain extended metal-on-semiconductor (DE_MOS) and low-voltage metal-on-semiconductor (LV_MOS) transistors and methods of manufacturing the same are provided. In one embodiment, the method includes implanting ions of a first-type at a first energy level in a drain portion of a first DE_MOS transistor in a DE_MOS region of a substrate to form the first DE_MOS transistor, and implanting ions of the first-type at a second energy level in a LV_MOS region of the…
Low power USB 2.0 subsystem
Granted: September 1, 2015
Patent Number:
9122288
USB physical interface subsystems are provided that include a protection circuit including a power supply interface and a plurality of pin interfaces, a pin identifier circuit in communication with the protection circuit for detecting a device coupling to a pin connected to one pin interface of the plurality of pin interfaces, a USB physical interface, and a dual power supply regulator configured to receive power via the power supply interface, to continuously supply a first voltage to…
Edge accuracy in a capacitive sense array
Granted: August 25, 2015
Patent Number:
9116581
A capacitive sense array configured to improve edge accuracy in detecting a presence of a conductive object is described. In one embodiment, a capacitive sense array includes at least a first set of sense elements having non-homogenous pitches disposes in a first longitudinal axis of the capacitive sense array. The pitch includes width of the sense elements and spacing between the sense elements.
Shallow bipolar junction transistor
Granted: August 18, 2015
Patent Number:
9111985
A shallow bipolar junction transistor comprising a high voltage n+ well implanted into a semiconductor substrate. The shallow bipolar junction transistor further comprises a bit line n+ implant (BNI) above the high voltage n+ well and an oxide nitride (ONO) layer above the high voltage n+ well. A portion of the ONO layer isolates the BNI from a shallow trench isolation (STI) region.
Method of fabricating a ferroelectric capacitor
Granted: August 18, 2015
Patent Number:
9111944
Ferroelectric capacitors used in ferroelectric random access memories (F-RAM) and methods for fabricating the same to reduce sidewall leakage are described. In one embodiment, the method includes depositing over a surface of a substrate, a ferro stack including a bottom electrode layer electrically coupled to a bottom electrode contact extending through the substrate, a top electrode layer and ferroelectric layer there between. A hard-mask is formed over the ferro stack, and a top…
Eliminating common mode noise in otuch applications
Granted: August 18, 2015
Patent Number:
9110552
A processing device scans, during a first operation, a first plurality of electrodes along a first axis in a capacitive sense array to generate a first plurality of signals corresponding to a mutual capacitance at electrode intersections of the capacitive sense array. During a second operation, the processing device scans a second plurality of electrodes along a second axis in the capacitive sense array to generate a second plurality of signals corresponding to the mutual capacitance at…
Method of ONO integration into logic CMOS flow
Granted: August 11, 2015
Patent Number:
9102522
An embodiment of a method of integration of a non-volatile memory device into a logic MOS flow is described. Generally, the method includes: forming a pad dielectric layer of a MOS device above a first region of a substrate; forming a channel of the memory device from a thin film of semiconducting material overlying a surface above a second region of the substrate, the channel connecting a source and drain of the memory device; forming a patterned dielectric stack overlying the channel…
SONOS type stacks for nonvolatile changetrap memory devices and methods to form the same
Granted: August 11, 2015
Patent Number:
9105740
A method for fabricating a nonvolatile charge trap memory device is described. The method includes forming a first oxide layer on a surface of a substrate. The first oxide layer is exposed to a first decoupled plasma nitridation process having a first bias. Subsequently, a charge-trapping layer is formed on the first oxide layer. The charge-trapping layer is exposed to an oxidation process and then to a second decoupled plasma nitridation process having a second, different, bias.
Full-bridge tip driver for active stylus
Granted: August 11, 2015
Patent Number:
9104251
A method and apparatus to increase a transmit (TX) signal generated by an active stylus without increasing the power consumption of the active stylus. In one aspect, the active stylus increases the amplitude of the TX signal. In another aspect, the active stylus increases the TX signal by providing the capacitance of a body of a user to the stylus.
Optical navigation module with capacitive sensor
Granted: August 11, 2015
Patent Number:
9103658
Optical navigation modules and methods of operating the same to sense relative movement between the optical navigation module and a tracking surface are provided. In one embodiment, the optical navigation module comprises: (i) a light source to illuminate at least a portion of a surface relative to which the optical navigation module is moved; (ii) an integrated circuit (IC) including a photo-detector array (PDA) to detect a light pattern propagated onto the PDA from the surface, and a…
